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@@ -58,7 +58,7 @@ static void __iomem *scu_base_addr(void)
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static DEFINE_SPINLOCK(boot_lock);
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-void __cpuinit platform_secondary_init(unsigned int cpu)
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+static void __cpuinit ux500_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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@@ -80,7 +80,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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spin_unlock(&boot_lock);
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}
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-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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+static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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@@ -145,7 +145,7 @@ static void __init wakeup_secondary(void)
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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-void __init smp_init_cpus(void)
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+static void __init ux500_smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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@@ -165,9 +165,19 @@ void __init smp_init_cpus(void)
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set_smp_cross_call(gic_raise_softirq);
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}
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-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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+static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base_addr());
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wakeup_secondary();
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}
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+
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+struct smp_operations ux500_smp_ops __initdata = {
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+ .smp_init_cpus = ux500_smp_init_cpus,
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+ .smp_prepare_cpus = ux500_smp_prepare_cpus,
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+ .smp_secondary_init = ux500_secondary_init,
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+ .smp_boot_secondary = ux500_boot_secondary,
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .cpu_die = ux500_cpu_die,
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+#endif
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+};
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