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@@ -298,11 +298,23 @@ static u32 unresettable_controller[] = {
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0x40800E11, /* Smart Array 5i */
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0x409C0E11, /* Smart Array 6400 */
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0x409D0E11, /* Smart Array 6400 EM */
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+ 0x40700E11, /* Smart Array 5300 */
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+ 0x40820E11, /* Smart Array 532 */
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+ 0x40830E11, /* Smart Array 5312 */
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+ 0x409A0E11, /* Smart Array 641 */
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+ 0x409B0E11, /* Smart Array 642 */
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+ 0x40910E11, /* Smart Array 6i */
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};
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/* List of controllers which cannot even be soft reset */
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static u32 soft_unresettable_controller[] = {
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0x40800E11, /* Smart Array 5i */
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+ 0x40700E11, /* Smart Array 5300 */
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+ 0x40820E11, /* Smart Array 532 */
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+ 0x40830E11, /* Smart Array 5312 */
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+ 0x409A0E11, /* Smart Array 641 */
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+ 0x409B0E11, /* Smart Array 642 */
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+ 0x40910E11, /* Smart Array 6i */
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/* Exclude 640x boards. These are two pci devices in one slot
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* which share a battery backed cache module. One controls the
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* cache, the other accesses the cache through the one that controls
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