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@@ -192,7 +192,7 @@ int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
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/* Sanity check SRQ size before proceeding */
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if (attr->max_wr > dev->limits.max_srq_wqes ||
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- attr->max_sge > dev->limits.max_sg)
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+ attr->max_sge > dev->limits.max_srq_sge)
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return -EINVAL;
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srq->max = attr->max_wr;
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@@ -660,6 +660,31 @@ int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
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return err;
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}
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+int mthca_max_srq_sge(struct mthca_dev *dev)
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+{
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+ if (mthca_is_memfree(dev))
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+ return dev->limits.max_sg;
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+
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+ /*
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+ * SRQ allocations are based on powers of 2 for Tavor,
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+ * (although they only need to be multiples of 16 bytes).
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+ *
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+ * Therefore, we need to base the max number of sg entries on
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+ * the largest power of 2 descriptor size that is <= to the
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+ * actual max WQE descriptor size, rather than return the
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+ * max_sg value given by the firmware (which is based on WQE
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+ * sizes as multiples of 16, not powers of 2).
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+ *
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+ * If SRQ implementation is changed for Tavor to be based on
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+ * multiples of 16, the calculation below can be deleted and
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+ * the FW max_sg value returned.
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+ */
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+ return min_t(int, dev->limits.max_sg,
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+ ((1 << (fls(dev->limits.max_desc_sz) - 1)) -
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+ sizeof (struct mthca_next_seg)) /
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+ sizeof (struct mthca_data_seg));
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+}
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+
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int __devinit mthca_init_srq_table(struct mthca_dev *dev)
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{
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int err;
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