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@@ -83,6 +83,7 @@ struct hdmi_resources {
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struct clk *sclk_pixel;
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struct clk *sclk_hdmiphy;
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struct clk *hdmiphy;
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+ struct clk *mout_hdmi;
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struct regulator_bulk_data *regul_bulk;
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int regul_count;
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};
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@@ -1112,7 +1113,7 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
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}
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clk_disable_unprepare(hdata->res.sclk_hdmi);
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- clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
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+ clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
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clk_prepare_enable(hdata->res.sclk_hdmi);
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/* enable HDMI and timing generator */
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@@ -1279,7 +1280,7 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
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}
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clk_disable_unprepare(hdata->res.sclk_hdmi);
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- clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
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+ clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
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clk_prepare_enable(hdata->res.sclk_hdmi);
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/* enable HDMI and timing generator */
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@@ -1305,7 +1306,7 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
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u32 reg;
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clk_disable_unprepare(hdata->res.sclk_hdmi);
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- clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
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+ clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
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clk_prepare_enable(hdata->res.sclk_hdmi);
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/* operation mode */
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@@ -1812,8 +1813,13 @@ static int hdmi_resources_init(struct hdmi_context *hdata)
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DRM_ERROR("failed to get clock 'hdmiphy'\n");
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goto fail;
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}
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+ res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
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+ if (IS_ERR(res->mout_hdmi)) {
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+ DRM_ERROR("failed to get clock 'mout_hdmi'\n");
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+ goto fail;
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+ }
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- clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
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+ clk_set_parent(res->mout_hdmi, res->sclk_pixel);
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res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
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sizeof(res->regul_bulk[0]), GFP_KERNEL);
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