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@@ -480,8 +480,6 @@ void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo,
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((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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- iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
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-
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
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fifo, true);
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@@ -506,8 +504,6 @@ void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id)
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trans_pcie->txq[txq_id].q.write_ptr = 0;
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iwl_trans_set_wr_ptrs(trans, txq_id, 0);
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- iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id));
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-
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iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
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0, false);
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}
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