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@@ -220,7 +220,13 @@ gx_configure_tft(struct fb_info *info)
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/* Set the dither control */
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/* Set the dither control */
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writel(0x70, par->vid_regs + GX_FP_DFC);
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writel(0x70, par->vid_regs + GX_FP_DFC);
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- /* Turn on the device */
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+ /* Enable the FP data and power (in case the BIOS didn't) */
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+
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+ fp = readl(par->vid_regs + GX_DCFG);
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+ fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
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+ writel(fp, par->vid_regs + GX_DCFG);
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+
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+ /* Unblank the panel */
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fp = readl(par->vid_regs + GX_FP_PM);
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fp = readl(par->vid_regs + GX_FP_PM);
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fp |= GX_FP_PM_P;
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fp |= GX_FP_PM_P;
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@@ -245,9 +251,12 @@ static void gx_configure_display(struct fb_info *info)
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writel(misc, par->vid_regs + GX_MISC);
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writel(misc, par->vid_regs + GX_MISC);
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/* Write the display configuration */
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/* Write the display configuration */
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-
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dcfg = readl(par->vid_regs + GX_DCFG);
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dcfg = readl(par->vid_regs + GX_DCFG);
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+ /* Disable hsync and vsync */
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+ dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
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+ writel(dcfg, par->vid_regs + GX_DCFG);
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+
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/* Clear bits from existing mode. */
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/* Clear bits from existing mode. */
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dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
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dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
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| GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
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| GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
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