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@@ -1255,7 +1255,9 @@ static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map)
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*/
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static int f10_early_channel_count(struct amd64_pvt *pvt)
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{
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+ int dbams[] = { DBAM0, DBAM1 };
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int err = 0, channels = 0;
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+ int i, j;
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u32 dbam;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
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@@ -1288,46 +1290,19 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
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* is more than just one DIMM present in unganged mode. Need to check
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* both controllers since DIMMs can be placed in either one.
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*/
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- channels = 0;
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- err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam);
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- if (err)
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- goto err_reg;
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-
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- if (DBAM_DIMM(0, dbam) > 0)
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- channels++;
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- if (DBAM_DIMM(1, dbam) > 0)
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- channels++;
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- if (DBAM_DIMM(2, dbam) > 0)
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- channels++;
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- if (DBAM_DIMM(3, dbam) > 0)
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- channels++;
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-
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- /* If more than 2 DIMMs are present, then we have 2 channels */
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- if (channels > 2)
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- channels = 2;
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- else if (channels == 0) {
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- /* No DIMMs on DCT0, so look at DCT1 */
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- err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam);
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+ for (i = 0; i < ARRAY_SIZE(dbams); i++) {
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+ err = pci_read_config_dword(pvt->dram_f2_ctl, dbams[i], &dbam);
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if (err)
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goto err_reg;
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- if (DBAM_DIMM(0, dbam) > 0)
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- channels++;
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- if (DBAM_DIMM(1, dbam) > 0)
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- channels++;
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- if (DBAM_DIMM(2, dbam) > 0)
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- channels++;
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- if (DBAM_DIMM(3, dbam) > 0)
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- channels++;
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-
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- if (channels > 2)
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- channels = 2;
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+ for (j = 0; j < 4; j++) {
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+ if (DBAM_DIMM(j, dbam) > 0) {
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+ channels++;
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+ break;
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+ }
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+ }
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}
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- /* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */
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- if (channels == 0)
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- channels = 1;
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-
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debugf0("MCT channel count: %d\n", channels);
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return channels;
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