|
@@ -442,7 +442,7 @@
|
|
#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
|
|
#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
|
|
#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
|
|
#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
|
|
#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
|
|
#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
|
|
-
|
|
|
|
|
|
+#define INT_44XX_MCPDM_IRQ (112 + IRQ_GIC_START)
|
|
|
|
|
|
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
|
|
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
|
|
* 16 MPUIO lines */
|
|
* 16 MPUIO lines */
|