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@@ -258,8 +258,10 @@ enum {
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* Doc says maximum transaction is 16KiB. If we had 16KiB en
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* route and 16KiB being queued, it boils down to needing
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* 32KiB.
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+ * 32KiB is insufficient for 1400 MTU, hence increasing
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+ * tx buffer size to 64KiB.
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*/
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- I2400M_TX_BUF_SIZE = 32768,
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+ I2400M_TX_BUF_SIZE = 65536,
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/**
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* Message header and payload descriptors have to be 16
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* aligned (16 + 4 * N = 16 * M). If we take that average sent
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@@ -274,6 +276,19 @@ enum {
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I2400M_TX_PLD_SIZE = sizeof(struct i2400m_msg_hdr)
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+ I2400M_TX_PLD_MAX * sizeof(struct i2400m_pld),
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I2400M_TX_SKIP = 0x80000000,
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+ /*
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+ * 16 byte aligned MAX_MTU + 4 byte payload prefix.
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+ */
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+ I2400M_MAX_MTU_ALIGN = 16,
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+ I2400M_TX_PDU_SIZE = I2400M_MAX_MTU % I2400M_MAX_MTU_ALIGN
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+ + I2400M_MAX_MTU + sizeof(struct i2400m_pl_data_hdr),
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+ /*
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+ * 256 byte aligned toal size of 12 PDUs including msg header,
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+ */
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+ I2400M_TX_PDU_ALIGN = 256,
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+ I2400M_TX_PDU_TOTAL_SIZE = ((I2400M_TX_PDU_SIZE * I2400M_TX_PLD_MAX
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+ + sizeof(struct i2400m_msg_hdr))/I2400M_TX_PDU_ALIGN + 1)
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+ * I2400M_TX_PDU_ALIGN * 2,
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};
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#define TAIL_FULL ((void *)~(unsigned long)NULL)
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@@ -874,6 +889,8 @@ int i2400m_tx_setup(struct i2400m *i2400m)
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INIT_WORK(&i2400m->wake_tx_ws, i2400m_wake_tx_work);
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i2400m->tx_sequence = 0;
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+ /* Warn if the calculated buffer size exceeds I2400M_TX_BUF_SIZE. */
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+ BUILD_BUG_ON(I2400M_TX_PDU_TOTAL_SIZE > I2400M_TX_BUF_SIZE);
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i2400m->tx_buf = kmalloc(I2400M_TX_BUF_SIZE, GFP_KERNEL);
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if (i2400m->tx_buf == NULL)
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result = -ENOMEM;
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