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@@ -368,6 +368,12 @@ static unsigned long clk_leafclk_recalc(struct clk *clk)
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return clk->parent->rate;
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}
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+int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ clk->rate = rate;
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+ return 0;
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+}
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+
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static unsigned long clk_pllclk_recalc(struct clk *clk)
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{
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u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
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@@ -506,6 +512,38 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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}
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EXPORT_SYMBOL(davinci_set_pllrate);
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+/**
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+ * davinci_set_refclk_rate() - Set the reference clock rate
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+ * @rate: The new rate.
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+ *
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+ * Sets the reference clock rate to a given value. This will most likely
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+ * result in the entire clock tree getting updated.
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+ *
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+ * This is used to support boards which use a reference clock different
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+ * than that used by default in <soc>.c file. The reference clock rate
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+ * should be updated early in the boot process; ideally soon after the
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+ * clock tree has been initialized once with the default reference clock
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+ * rate (davinci_common_init()).
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+ *
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+ * Returns 0 on success, error otherwise.
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+ */
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+int davinci_set_refclk_rate(unsigned long rate)
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+{
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+ struct clk *refclk;
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+
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+ refclk = clk_get(NULL, "ref");
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+ if (IS_ERR(refclk)) {
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+ pr_err("%s: failed to get reference clock.\n", __func__);
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+ return PTR_ERR(refclk);
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+ }
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+
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+ clk_set_rate(refclk, rate);
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+
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+ clk_put(refclk);
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+
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+ return 0;
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+}
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+
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int __init davinci_clk_init(struct clk_lookup *clocks)
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{
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struct clk_lookup *c;
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