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@@ -1,5 +1,6 @@
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/*
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- * Copyright (C) 2012 Altera Corporation <www.altera.com>
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+ * Copyright 2011-2012 Calxeda, Inc.
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+ * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -11,41 +12,161 @@
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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+ * Based from clk-highbank.c
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+ *
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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-#define SOCFPGA_OSC1_CLK 10000000
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-#define SOCFPGA_MPU_CLK 800000000
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-#define SOCFPGA_MAIN_QSPI_CLK 432000000
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-#define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000
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-#define SOCFPGA_S2F_USR_CLK 125000000
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+/* Clock Manager offsets */
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+#define CLKMGR_CTRL 0x0
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+#define CLKMGR_BYPASS 0x4
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-void __init socfpga_init_clocks(void)
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+/* Clock bypass bits */
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+#define MAINPLL_BYPASS (1<<0)
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+#define SDRAMPLL_BYPASS (1<<1)
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+#define SDRAMPLL_SRC_BYPASS (1<<2)
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+#define PERPLL_BYPASS (1<<3)
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+#define PERPLL_SRC_BYPASS (1<<4)
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+
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+#define SOCFPGA_PLL_BG_PWRDWN 0
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+#define SOCFPGA_PLL_EXT_ENA 1
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+#define SOCFPGA_PLL_PWR_DOWN 2
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+#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
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+#define SOCFPGA_PLL_DIVF_SHIFT 3
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+#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
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+#define SOCFPGA_PLL_DIVQ_SHIFT 16
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+
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+extern void __iomem *clk_mgr_base_addr;
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+
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+struct socfpga_clk {
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+ struct clk_gate hw;
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+ char *parent_name;
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+ char *clk_name;
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+ u32 fixed_div;
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+};
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+#define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
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+
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+static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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+ unsigned long parent_rate)
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{
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+ struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
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+ unsigned long divf, divq, vco_freq, reg;
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+ unsigned long bypass;
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+
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+ reg = readl(socfpgaclk->hw.reg);
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+ bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
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+ if (bypass & MAINPLL_BYPASS)
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+ return parent_rate;
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+
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+ divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
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+ divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
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+ vco_freq = parent_rate * (divf + 1);
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+ return vco_freq / (1 + divq);
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+}
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+
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+
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+static struct clk_ops clk_pll_ops = {
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+ .recalc_rate = clk_pll_recalc_rate,
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+};
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+
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+static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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+ unsigned long parent_rate)
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+{
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+ struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
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+ u32 div;
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+
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+ if (socfpgaclk->fixed_div)
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+ div = socfpgaclk->fixed_div;
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+ else
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+ div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
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+
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+ return parent_rate / div;
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+}
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+
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+static const struct clk_ops periclk_ops = {
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+ .recalc_rate = clk_periclk_recalc_rate,
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+};
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+
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+static __init struct clk *socfpga_clk_init(struct device_node *node,
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+ const struct clk_ops *ops)
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+{
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+ u32 reg;
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struct clk *clk;
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+ struct socfpga_clk *socfpga_clk;
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+ const char *clk_name = node->name;
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+ const char *parent_name;
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+ struct clk_init_data init;
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+ int rc;
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+ u32 fixed_div;
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+
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+ rc = of_property_read_u32(node, "reg", ®);
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+ if (WARN_ON(rc))
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+ return NULL;
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+
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+ socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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+ if (WARN_ON(!socfpga_clk))
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+ return NULL;
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+
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+ socfpga_clk->hw.reg = clk_mgr_base_addr + reg;
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+
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+ rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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+ if (rc)
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+ socfpga_clk->fixed_div = 0;
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+ else
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+ socfpga_clk->fixed_div = fixed_div;
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+
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+ of_property_read_string(node, "clock-output-names", &clk_name);
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+
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+ init.name = clk_name;
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+ init.ops = ops;
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+ init.flags = 0;
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+ parent_name = of_clk_get_parent_name(node, 0);
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+ init.parent_names = &parent_name;
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+ init.num_parents = 1;
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- clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
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- clk_register_clkdev(clk, "osc1_clk", NULL);
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+ socfpga_clk->hw.hw.init = &init;
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- clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
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- clk_register_clkdev(clk, "mpu_clk", NULL);
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+ if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
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+ strcmp(clk_name, "sdram_pll")) {
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+ socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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+ clk_pll_ops.enable = clk_gate_ops.enable;
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+ clk_pll_ops.disable = clk_gate_ops.disable;
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+ }
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- clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
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- clk_register_clkdev(clk, "main_clk", NULL);
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+ clk = clk_register(NULL, &socfpga_clk->hw.hw);
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+ if (WARN_ON(IS_ERR(clk))) {
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+ kfree(socfpga_clk);
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+ return NULL;
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+ }
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+ rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ return clk;
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+}
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- clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
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- clk_register_clkdev(clk, "dbg_base_clk", NULL);
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+static void __init socfpga_pll_init(struct device_node *node)
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+{
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+ socfpga_clk_init(node, &clk_pll_ops);
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+}
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+CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);
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- clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
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- clk_register_clkdev(clk, "main_qspi_clk", NULL);
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+static void __init socfpga_periph_init(struct device_node *node)
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+{
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+ socfpga_clk_init(node, &periclk_ops);
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+}
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+CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
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- clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
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- clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
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+void __init socfpga_init_clocks(void)
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+{
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+ struct clk *clk;
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+ int ret;
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- clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
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- clk_register_clkdev(clk, "s2f_usr_clk", NULL);
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+ clk = clk_register_fixed_factor(NULL, "smp_twd", "mpuclk", 0, 1, 4);
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+ ret = clk_register_clkdev(clk, NULL, "smp_twd");
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+ if (ret)
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+ pr_err("smp_twd alias not registered\n");
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}
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