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@@ -2593,7 +2593,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
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/* Write PCDAC values on hw */
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static void
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-ath5k_setup_pcdac_table(struct ath5k_hw *ah)
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+ath5k_write_pcdac_table(struct ath5k_hw *ah)
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{
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u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
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int i;
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@@ -2742,7 +2742,7 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
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/* Write PDADC values on hw */
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static void
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-ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
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+ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
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{
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struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
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@@ -2957,8 +2957,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
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(s16) pcinfo_R->freq,
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pcinfo_L->max_pwr, pcinfo_R->max_pwr);
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- /* We are ready to go, fill PCDAC/PDADC
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- * table and write settings on hardware */
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+ /* Fill PCDAC/PDADC table */
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switch (type) {
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case AR5K_PWRTABLE_LINEAR_PCDAC:
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/* For RF5112 we can have one or two curves
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@@ -2971,9 +2970,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
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* match max power value with max
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* table index */
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ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
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-
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- /* Write settings on hw */
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- ath5k_setup_pcdac_table(ah);
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break;
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case AR5K_PWRTABLE_PWR_TO_PCDAC:
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/* We are done for RF5111 since it has only
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@@ -2983,9 +2979,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
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/* No rate powertable adjustment for RF5111 */
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ah->ah_txpower.txp_min_idx = 0;
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ah->ah_txpower.txp_offset = 0;
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-
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- /* Write settings on hw */
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- ath5k_setup_pcdac_table(ah);
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break;
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case AR5K_PWRTABLE_PWR_TO_PDADC:
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/* Set PDADC boundaries and fill
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@@ -2993,9 +2986,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
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ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
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ee->ee_pd_gains[ee_mode]);
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- /* Write settings on hw */
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- ath5k_setup_pwr_to_pdadc_table(ah, ee_mode);
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-
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/* Set txp.offset, note that table_min
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* can be negative */
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ah->ah_txpower.txp_offset = table_min[0];
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@@ -3009,6 +2999,15 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
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return 0;
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}
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+/* Write power table for current channel to hw */
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+static void
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+ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
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+{
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+ if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
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+ ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
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+ else
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+ ath5k_write_pcdac_table(ah);
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+}
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/*
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* Per-rate tx power setting
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@@ -3159,11 +3158,10 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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ee_mode, type);
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if (ret)
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return ret;
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- /* Write cached table on hw */
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- } else if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
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- ath5k_setup_pwr_to_pdadc_table(ah, ee_mode);
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- else
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- ath5k_setup_pcdac_table(ah);
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+ }
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+
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+ /* Write table on hw */
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+ ath5k_write_channel_powertable(ah, ee_mode, type);
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/* Limit max power if we have a CTL available */
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ath5k_get_max_ctl_power(ah, channel);
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