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@@ -51,23 +51,23 @@ const char *get_system_type(void)
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void __init plat_timer_setup(struct irqaction *irq)
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{
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/* Load timer value for HZ (TCLK is 50MHz) */
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- GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS);
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+ GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
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/* Enable timer */
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- GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
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+ GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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/* Register interrupt */
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setup_irq(COBALT_GALILEO_IRQ, irq);
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/* Enable interrupt */
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- GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
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+ GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
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}
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extern struct pci_ops gt64111_pci_ops;
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static struct resource cobalt_mem_resource = {
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- .start = GT64111_MEM_BASE,
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- .end = GT64111_MEM_END,
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+ .start = GT_DEF_PCI0_MEM0_BASE,
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+ .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
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.name = "PCI memory",
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.flags = IORESOURCE_MEM
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};
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@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
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.mem_resource = &cobalt_mem_resource,
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.mem_offset = 0,
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.io_resource = &cobalt_io_resource,
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- .io_offset = 0 - GT64111_IO_BASE
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+ .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
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};
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void __init plat_mem_setup(void)
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@@ -128,7 +128,7 @@ void __init plat_mem_setup(void)
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_machine_halt = cobalt_machine_halt;
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pm_power_off = cobalt_machine_power_off;
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- set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
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+ set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
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/* I/O port resource must include UART and LCD/buttons */
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ioport_resource.end = 0x0fffffff;
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@@ -139,7 +139,7 @@ void __init plat_mem_setup(void)
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/* Read the cobalt id register out of the PCI config space */
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PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
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- cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
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+ cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
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cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
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cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
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