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@@ -96,16 +96,16 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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- } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
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- IS_GM45(dev)) {
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+ } else if (IS_MOBILE(dev)) {
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uint32_t dcc;
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- /* On 915-945 and GM965, channel interleave by the CPU is
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- * determined by DCC. The CPU will alternate based on bit 6
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- * in interleaved mode, and the GPU will then also alternate
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- * on bit 6, 9, and 10 for X, but the CPU may also optionally
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- * alternate based on bit 17 (XOR not disabled and XOR
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- * bit == 17).
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+ /* On mobile 9xx chipsets, channel interleave by the CPU is
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+ * determined by DCC. For single-channel, neither the CPU
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+ * nor the GPU do swizzling. For dual channel interleaved,
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+ * the GPU's interleave is bit 9 and 10 for X tiled, and bit
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+ * 9 for Y tiled. The CPU's interleave is independent, and
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+ * can be based on either bit 11 (haven't seen this yet) or
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+ * bit 17 (common).
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*/
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dcc = I915_READ(DCC);
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switch (dcc & DCC_ADDRESSING_MODE_MASK) {
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@@ -115,19 +115,18 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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break;
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case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
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- if (IS_I915G(dev) || IS_I915GM(dev) ||
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- dcc & DCC_CHANNEL_XOR_DISABLE) {
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+ if (dcc & DCC_CHANNEL_XOR_DISABLE) {
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+ /* This is the base swizzling by the GPU for
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+ * tiled buffers.
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+ */
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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- } else if ((IS_I965GM(dev) || IS_GM45(dev)) &&
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- (dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
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- /* GM965/GM45 does either bit 11 or bit 17
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- * swizzling.
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- */
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+ } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
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+ /* Bit 11 swizzling by the CPU in addition. */
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swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
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swizzle_y = I915_BIT_6_SWIZZLE_9_11;
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} else {
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- /* Bit 17 or perhaps other swizzling */
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+ /* Bit 17 swizzling by the CPU in addition. */
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swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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}
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