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@@ -444,6 +444,18 @@ static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
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EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
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EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
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EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
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+ EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
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+ EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
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+ EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
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+ EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
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+ EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
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+ EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
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+ EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
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+ EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
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+ EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
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+ EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
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+ EF10_DMA_STAT(rx_dp_emerg_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
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+ EF10_DMA_STAT(rx_dp_emerg_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
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};
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#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
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@@ -498,15 +510,38 @@ static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
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#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
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(1ULL << EF10_STAT_rx_length_error))
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+/* These statistics are only provided if the firmware supports the
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+ * capability PM_AND_RXDP_COUNTERS.
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+ */
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+#define HUNT_PM_AND_RXDP_STAT_MASK ( \
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+ (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
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+ (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
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+ (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
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+ (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
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+ (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
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+ (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
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+ (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
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+ (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
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+ (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
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+ (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
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+ (1ULL << EF10_STAT_rx_dp_emerg_fetch) | \
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+ (1ULL << EF10_STAT_rx_dp_emerg_wait))
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+
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static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
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{
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u64 raw_mask = HUNT_COMMON_STAT_MASK;
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u32 port_caps = efx_mcdi_phy_get_caps(efx);
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+ struct efx_ef10_nic_data *nic_data = efx->nic_data;
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if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
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raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
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else
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raw_mask |= HUNT_10G_ONLY_STAT_MASK;
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+
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+ if (nic_data->datapath_caps &
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+ (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
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+ raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
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+
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return raw_mask;
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}
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