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@@ -38,6 +38,14 @@
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};
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};
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+ gic: interrupt-controller@48241000 {
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+ compatible = "arm,cortex-a9-gic";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = <0x48241000 0x1000>,
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+ <0x48240100 0x0100>;
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+ };
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+
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L2: l2-cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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@@ -76,30 +84,6 @@
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/*
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* XXX: Use a flat representation of the OMAP4 interconnect.
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* The real OMAP interconnect network is quite complex.
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- *
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- * MPU -+-- MPU_PRIVATE - GIC, L2
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- * |
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- * +----------------+----------+
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- * | | |
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- * + +- EMIF - DDR |
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- * | | |
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- * | + +--------+
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- * | | |
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- * | +- L4_ABE - AESS, MCBSP, TIMERs...
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- * | |
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- * +- L3_MAIN --+- L4_CORE - IPs...
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- * |
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- * +- L4_PER - IPs...
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- * |
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- * +- L4_CFG -+- L4_WKUP - IPs...
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- * | |
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- * | +- IPs...
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- * +- IPU ----+
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- * | |
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- * +- DSP ----+
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- * | |
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- * +- DSS ----+
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- *
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* Since that will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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@@ -111,14 +95,6 @@
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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- gic: interrupt-controller@48241000 {
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- compatible = "arm,cortex-a9-gic";
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- reg = <0x48241000 0x1000>,
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- <0x48240100 0x0100>;
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- };
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-
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gpio1: gpio@4a310000 {
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio1";
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