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@@ -322,22 +322,8 @@ static struct omap_clk omap34xx_clks[] = {
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#define MAX_DPLL_WAIT_TRIES 1000000
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-#define MIN_SDRC_DLL_LOCK_FREQ 83000000
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-
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#define CYCLES_PER_MHZ 1000000
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-/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
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-#define SDRC_MPURATE_SCALE 8
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-
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-/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
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-#define SDRC_MPURATE_BASE_SHIFT 9
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-
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-/*
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- * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
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- * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
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- */
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-#define SDRC_MPURATE_LOOPS 96
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-
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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