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@@ -304,9 +304,9 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
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WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
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}
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- } else if (ASIC_IS_DCE3(rdev)) {
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+ } else {
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/* according to the reg specs, this should DCE3.2 only, but in
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- * practice it seems to cover DCE3.0/3.1 as well.
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+ * practice it seems to cover DCE2.0/3.0/3.1 as well.
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*/
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if (dig->dig_encoder == 0) {
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WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
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@@ -317,10 +317,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
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}
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- } else {
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- /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
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- WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
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- AUDIO_DTO_MODULE(clock / 10));
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}
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}
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