|
@@ -1468,8 +1468,8 @@ static struct radeon_asic btc_asic = {
|
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
|
- .get_pcie_lanes = NULL,
|
|
|
- .set_pcie_lanes = NULL,
|
|
|
+ .get_pcie_lanes = &r600_get_pcie_lanes,
|
|
|
+ .set_pcie_lanes = &r600_set_pcie_lanes,
|
|
|
.set_clock_gating = NULL,
|
|
|
.set_uvd_clocks = &evergreen_set_uvd_clocks,
|
|
|
},
|
|
@@ -1607,8 +1607,8 @@ static struct radeon_asic cayman_asic = {
|
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
|
- .get_pcie_lanes = NULL,
|
|
|
- .set_pcie_lanes = NULL,
|
|
|
+ .get_pcie_lanes = &r600_get_pcie_lanes,
|
|
|
+ .set_pcie_lanes = &r600_set_pcie_lanes,
|
|
|
.set_clock_gating = NULL,
|
|
|
.set_uvd_clocks = &evergreen_set_uvd_clocks,
|
|
|
},
|
|
@@ -1885,8 +1885,8 @@ static struct radeon_asic si_asic = {
|
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
|
- .get_pcie_lanes = NULL,
|
|
|
- .set_pcie_lanes = NULL,
|
|
|
+ .get_pcie_lanes = &r600_get_pcie_lanes,
|
|
|
+ .set_pcie_lanes = &r600_set_pcie_lanes,
|
|
|
.set_clock_gating = NULL,
|
|
|
.set_uvd_clocks = &si_set_uvd_clocks,
|
|
|
},
|