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@@ -699,7 +699,7 @@ void __cpuinit mp_register_lapic(u8 id, u8 enabled)
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static struct mp_ioapic_routing {
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int apic_id;
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- int gsi_start;
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+ int gsi_base;
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int gsi_end;
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u32 pin_programmed[4];
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} mp_ioapic_routing[MAX_IO_APICS];
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@@ -710,7 +710,7 @@ static int mp_find_ioapic(int gsi)
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/* Find the IOAPIC that manages this GSI. */
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for (i = 0; i < nr_ioapics; i++) {
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- if ((gsi >= mp_ioapic_routing[i].gsi_start)
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+ if ((gsi >= mp_ioapic_routing[i].gsi_base)
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&& (gsi <= mp_ioapic_routing[i].gsi_end))
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return i;
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}
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@@ -755,14 +755,14 @@ void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
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* and to prevent reprogramming of IOAPIC pins (PCI IRQs).
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*/
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mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
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- mp_ioapic_routing[idx].gsi_start = gsi_base;
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+ mp_ioapic_routing[idx].gsi_base = gsi_base;
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mp_ioapic_routing[idx].gsi_end = gsi_base +
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io_apic_get_redir_entries(idx);
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printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
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"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
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mp_ioapics[idx].mpc_apicaddr,
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- mp_ioapic_routing[idx].gsi_start,
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+ mp_ioapic_routing[idx].gsi_base,
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mp_ioapic_routing[idx].gsi_end);
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nr_ioapics++;
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@@ -780,7 +780,7 @@ void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
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ioapic = mp_find_ioapic(gsi);
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if (ioapic < 0)
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return;
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- pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
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+ pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
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/*
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* TBD: This check is for faulty timer entries, where the override
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@@ -892,7 +892,7 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
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return gsi;
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}
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- ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
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+ ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
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/*
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* Avoid pin reprogramming. PRTs typically include entries
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