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@@ -146,8 +146,9 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
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u32 mask, st;
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/* XXX read mask from RAM? */
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- mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
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- st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
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+ mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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+ irqen_offs);
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+ st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
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return mask & st;
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}
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@@ -179,7 +180,7 @@ void omap44xx_prm_read_pending_irqs(unsigned long *events)
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*/
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void omap44xx_prm_ocp_barrier(void)
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{
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- omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_REVISION_PRM_OFFSET);
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}
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@@ -197,19 +198,19 @@ void omap44xx_prm_ocp_barrier(void)
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void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] =
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- omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
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saved_mask[1] =
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- omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
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- omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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- omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
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/* OCP barrier */
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- omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_REVISION_PRM_OFFSET);
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}
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@@ -225,9 +226,9 @@ void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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*/
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void omap44xx_prm_restore_irqen(u32 *saved_mask)
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{
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- omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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- omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
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+ omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
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}
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