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@@ -408,17 +408,25 @@ void __init r8a7778_init_irq_extpin(int irlm)
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&irqpin_platform_data, sizeof(irqpin_platform_data));
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}
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+void __init r8a7778_init_delay(void)
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+{
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+ shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
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+}
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+
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+#ifdef CONFIG_USE_OF
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#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
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#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
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#define INT2NTSR0 0x00018 /* 0xfe700018 */
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#define INT2NTSR1 0x0002c /* 0xfe70002c */
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-static void __init r8a7778_init_irq_common(void)
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+void __init r8a7778_init_irq_dt(void)
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{
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void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
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BUG_ON(!base);
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+ irqchip_init();
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+
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/* route all interrupts to ARM */
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__raw_writel(0x73ffffff, base + INT2NTSR0);
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__raw_writel(0xffffffff, base + INT2NTSR1);
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@@ -430,33 +438,6 @@ static void __init r8a7778_init_irq_common(void)
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iounmap(base);
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}
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-void __init r8a7778_init_irq(void)
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-{
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- void __iomem *gic_dist_base;
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- void __iomem *gic_cpu_base;
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-
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- gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
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- gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
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- BUG_ON(!gic_dist_base || !gic_cpu_base);
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-
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- /* use GIC to handle interrupts */
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- gic_init(0, 29, gic_dist_base, gic_cpu_base);
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-
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- r8a7778_init_irq_common();
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-}
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-
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-void __init r8a7778_init_delay(void)
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-{
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- shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
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-}
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-
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-#ifdef CONFIG_USE_OF
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-void __init r8a7778_init_irq_dt(void)
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-{
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- irqchip_init();
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- r8a7778_init_irq_common();
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-}
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-
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static const char *r8a7778_compat_dt[] __initdata = {
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"renesas,r8a7778",
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NULL,
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