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@@ -13,27 +13,19 @@
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#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
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-static int omap1_clk_enable_generic(struct clk * clk);
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-static void omap1_clk_disable_generic(struct clk * clk);
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static void omap1_ckctl_recalc(struct clk * clk);
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static void omap1_watchdog_recalc(struct clk * clk);
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static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
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static void omap1_sossi_recalc(struct clk *clk);
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static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
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-static int omap1_clk_enable_dsp_domain(struct clk * clk);
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static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
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-static void omap1_clk_disable_dsp_domain(struct clk * clk);
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static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
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static void omap1_uart_recalc(struct clk * clk);
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-static int omap1_clk_enable_uart_functional(struct clk * clk);
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-static void omap1_clk_disable_uart_functional(struct clk * clk);
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static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
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static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
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static void omap1_init_ext_clk(struct clk * clk);
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static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
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static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
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-static int omap1_clk_enable(struct clk *clk);
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-static void omap1_clk_disable(struct clk *clk);
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struct mpu_rate {
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unsigned long rate;
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@@ -152,39 +144,37 @@ static struct mpu_rate rate_table[] = {
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static struct clk ck_ref = {
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.name = "ck_ref",
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+ .ops = &clkops_generic,
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk ck_dpll1 = {
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.name = "ck_dpll1",
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+ .ops = &clkops_generic,
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct arm_idlect1_clk ck_dpll1out = {
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.clk = {
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.name = "ck_dpll1out",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
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ENABLE_REG_32BIT | RATE_PROPAGATES,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_CKOUT_ARM,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 12,
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};
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static struct clk sossi_ck = {
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.name = "ck_sossi",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1out.clk,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
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ENABLE_REG_32BIT,
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@@ -192,25 +182,23 @@ static struct clk sossi_ck = {
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.enable_bit = 16,
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.recalc = &omap1_sossi_recalc,
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.set_rate = &omap1_set_sossi_rate,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk arm_ck = {
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.name = "arm_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
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ALWAYS_ENABLED,
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.rate_offset = CKCTL_ARMDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct arm_idlect1_clk armper_ck = {
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.clk = {
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.name = "armper_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | RATE_CKCTL |
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@@ -219,34 +207,30 @@ static struct arm_idlect1_clk armper_ck = {
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.enable_bit = EN_PERCK,
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.rate_offset = CKCTL_PERDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 2,
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};
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static struct clk arm_gpio_ck = {
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.name = "arm_gpio_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_GPIOCK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct arm_idlect1_clk armxor_ck = {
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.clk = {
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.name = "armxor_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_XORPCK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 1,
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};
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@@ -254,14 +238,13 @@ static struct arm_idlect1_clk armxor_ck = {
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static struct arm_idlect1_clk armtim_ck = {
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.clk = {
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.name = "armtim_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_TIMCK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 9,
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};
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@@ -269,20 +252,20 @@ static struct arm_idlect1_clk armtim_ck = {
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static struct arm_idlect1_clk armwdt_ck = {
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.clk = {
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.name = "armwdt_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_WDTCK,
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.recalc = &omap1_watchdog_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 0,
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};
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static struct clk arminth_ck16xx = {
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.name = "arminth_ck",
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+ .ops = &clkops_generic,
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.parent = &arm_ck,
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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.recalc = &followparent_recalc,
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@@ -291,12 +274,11 @@ static struct clk arminth_ck16xx = {
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*
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* 1510 version is in TC clocks.
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*/
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk dsp_ck = {
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.name = "dsp_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL,
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@@ -304,23 +286,21 @@ static struct clk dsp_ck = {
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.enable_bit = EN_DSPCK,
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.rate_offset = CKCTL_DSPDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk dspmmu_ck = {
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.name = "dspmmu_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL | ALWAYS_ENABLED,
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.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk dspper_ck = {
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.name = "dspper_ck",
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+ .ops = &clkops_dspck,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL | VIRTUAL_IO_ADDRESS,
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@@ -329,38 +309,35 @@ static struct clk dspper_ck = {
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.rate_offset = CKCTL_PERDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc_dsp_domain,
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.set_rate = &omap1_clk_set_rate_dsp_domain,
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- .enable = &omap1_clk_enable_dsp_domain,
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- .disable = &omap1_clk_disable_dsp_domain,
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};
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static struct clk dspxor_ck = {
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.name = "dspxor_ck",
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+ .ops = &clkops_dspck,
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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VIRTUAL_IO_ADDRESS,
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.enable_reg = DSP_IDLECT2,
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.enable_bit = EN_XORPCK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_dsp_domain,
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- .disable = &omap1_clk_disable_dsp_domain,
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};
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static struct clk dsptim_ck = {
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.name = "dsptim_ck",
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+ .ops = &clkops_dspck,
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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VIRTUAL_IO_ADDRESS,
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.enable_reg = DSP_IDLECT2,
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.enable_bit = EN_DSPTIMCK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_dsp_domain,
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- .disable = &omap1_clk_disable_dsp_domain,
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};
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/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
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static struct arm_idlect1_clk tc_ck = {
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.clk = {
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.name = "tc_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
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@@ -368,14 +345,13 @@ static struct arm_idlect1_clk tc_ck = {
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ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
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.rate_offset = CKCTL_TCDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 6,
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};
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static struct clk arminth_ck1510 = {
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.name = "arminth_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
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ALWAYS_ENABLED,
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@@ -384,86 +360,77 @@ static struct clk arminth_ck1510 = {
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*
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* 16xx version is in MPU clocks.
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*/
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk tipb_ck = {
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/* No-idle controlled by "tc_ck" */
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.name = "tipb_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
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ALWAYS_ENABLED,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk l3_ocpi_ck = {
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/* No-idle controlled by "tc_ck" */
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.name = "l3_ocpi_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = (void __iomem *)ARM_IDLECT3,
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.enable_bit = EN_OCPI_CK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk tc1_ck = {
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.name = "tc1_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = (void __iomem *)ARM_IDLECT3,
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.enable_bit = EN_TC1_CK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk tc2_ck = {
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.name = "tc2_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = (void __iomem *)ARM_IDLECT3,
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.enable_bit = EN_TC2_CK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk dma_ck = {
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/* No-idle controlled by "tc_ck" */
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.name = "dma_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk dma_lcdfree_ck = {
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.name = "dma_lcdfree_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct arm_idlect1_clk api_ck = {
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.clk = {
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.name = "api_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_APICK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 8,
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};
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@@ -471,51 +438,48 @@ static struct arm_idlect1_clk api_ck = {
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static struct arm_idlect1_clk lb_ck = {
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.clk = {
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.name = "lb_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
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CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_LBCK,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 4,
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};
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static struct clk rhea1_ck = {
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.name = "rhea1_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk rhea2_ck = {
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.name = "rhea2_ck",
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+ .ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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.recalc = &followparent_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct clk lcd_ck_16xx = {
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.name = "lcd_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_LCDCK,
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.rate_offset = CKCTL_LCDDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct arm_idlect1_clk lcd_ck_1510 = {
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.clk = {
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.name = "lcd_ck",
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+ .ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
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RATE_CKCTL | CLOCK_IDLE_CONTROL,
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@@ -523,14 +487,13 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
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.enable_bit = EN_LCDCK,
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.rate_offset = CKCTL_LCDDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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},
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.idlect_shift = 3,
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};
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static struct clk uart1_1510 = {
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.name = "uart1_ck",
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+ .ops = &clkops_generic,
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/* Direct from ULPD, no real parent */
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|
.parent = &armper_ck.clk,
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.rate = 12000000,
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@@ -541,13 +504,12 @@ static struct clk uart1_1510 = {
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.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
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.set_rate = &omap1_set_uart_rate,
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.recalc = &omap1_uart_recalc,
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- .enable = &omap1_clk_enable_generic,
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- .disable = &omap1_clk_disable_generic,
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};
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static struct uart_clk uart1_16xx = {
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|
.clk = {
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.name = "uart1_ck",
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+ .ops = &clkops_uart,
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|
/* Direct from ULPD, no real parent */
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|
.parent = &armper_ck.clk,
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|
.rate = 48000000,
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|
@@ -555,14 +517,13 @@ static struct uart_clk uart1_16xx = {
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ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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|
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
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|
.enable_bit = 29,
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|
- .enable = &omap1_clk_enable_uart_functional,
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|
- .disable = &omap1_clk_disable_uart_functional,
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|
},
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|
.sysc_addr = 0xfffb0054,
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|
};
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|
|
|
|
static struct clk uart2_ck = {
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|
|
.name = "uart2_ck",
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|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no real parent */
|
|
|
.parent = &armper_ck.clk,
|
|
|
.rate = 12000000,
|
|
@@ -573,12 +534,11 @@ static struct clk uart2_ck = {
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|
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
|
|
|
.set_rate = &omap1_set_uart_rate,
|
|
|
.recalc = &omap1_uart_recalc,
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|
|
- .enable = &omap1_clk_enable_generic,
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|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk uart3_1510 = {
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|
|
.name = "uart3_ck",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no real parent */
|
|
|
.parent = &armper_ck.clk,
|
|
|
.rate = 12000000,
|
|
@@ -589,13 +549,12 @@ static struct clk uart3_1510 = {
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|
|
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
|
|
|
.set_rate = &omap1_set_uart_rate,
|
|
|
.recalc = &omap1_uart_recalc,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct uart_clk uart3_16xx = {
|
|
|
.clk = {
|
|
|
.name = "uart3_ck",
|
|
|
+ .ops = &clkops_uart,
|
|
|
/* Direct from ULPD, no real parent */
|
|
|
.parent = &armper_ck.clk,
|
|
|
.rate = 48000000,
|
|
@@ -603,38 +562,35 @@ static struct uart_clk uart3_16xx = {
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|
|
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
|
|
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
|
|
|
.enable_bit = 31,
|
|
|
- .enable = &omap1_clk_enable_uart_functional,
|
|
|
- .disable = &omap1_clk_disable_uart_functional,
|
|
|
},
|
|
|
.sysc_addr = 0xfffb9854,
|
|
|
};
|
|
|
|
|
|
static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
|
|
|
.name = "usb_clko",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent */
|
|
|
.rate = 6000000,
|
|
|
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
|
|
|
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
|
|
|
.enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
|
|
|
.enable_bit = USB_MCLK_EN_BIT,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk usb_hhc_ck1510 = {
|
|
|
.name = "usb_hhc_ck",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent */
|
|
|
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
|
|
|
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
|
|
|
RATE_FIXED | ENABLE_REG_32BIT,
|
|
|
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
|
|
|
.enable_bit = USB_HOST_HHC_UHOST_EN,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk usb_hhc_ck16xx = {
|
|
|
.name = "usb_hhc_ck",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent */
|
|
|
.rate = 48000000,
|
|
|
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
|
@@ -642,34 +598,31 @@ static struct clk usb_hhc_ck16xx = {
|
|
|
RATE_FIXED | ENABLE_REG_32BIT,
|
|
|
.enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
|
|
|
.enable_bit = 8 /* UHOST_EN */,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk usb_dc_ck = {
|
|
|
.name = "usb_dc_ck",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent */
|
|
|
.rate = 48000000,
|
|
|
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
|
|
|
.enable_reg = (void __iomem *)SOFT_REQ_REG,
|
|
|
.enable_bit = 4,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk mclk_1510 = {
|
|
|
.name = "mclk",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
|
|
.rate = 12000000,
|
|
|
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
|
|
|
.enable_reg = (void __iomem *)SOFT_REQ_REG,
|
|
|
.enable_bit = 6,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk mclk_16xx = {
|
|
|
.name = "mclk",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
|
|
.flags = CLOCK_IN_OMAP16XX,
|
|
|
.enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
|
|
@@ -677,21 +630,19 @@ static struct clk mclk_16xx = {
|
|
|
.set_rate = &omap1_set_ext_clk_rate,
|
|
|
.round_rate = &omap1_round_ext_clk_rate,
|
|
|
.init = &omap1_init_ext_clk,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk bclk_1510 = {
|
|
|
.name = "bclk",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
|
|
.rate = 12000000,
|
|
|
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk bclk_16xx = {
|
|
|
.name = "bclk",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
|
|
.flags = CLOCK_IN_OMAP16XX,
|
|
|
.enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
|
|
@@ -699,12 +650,11 @@ static struct clk bclk_16xx = {
|
|
|
.set_rate = &omap1_set_ext_clk_rate,
|
|
|
.round_rate = &omap1_round_ext_clk_rate,
|
|
|
.init = &omap1_init_ext_clk,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk mmc1_ck = {
|
|
|
.name = "mmc_ck",
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
|
|
.parent = &armper_ck.clk,
|
|
|
.rate = 48000000,
|
|
@@ -713,13 +663,12 @@ static struct clk mmc1_ck = {
|
|
|
CLOCK_NO_IDLE_PARENT,
|
|
|
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
|
|
|
.enable_bit = 23,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk mmc2_ck = {
|
|
|
.name = "mmc_ck",
|
|
|
.id = 1,
|
|
|
+ .ops = &clkops_generic,
|
|
|
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
|
|
.parent = &armper_ck.clk,
|
|
|
.rate = 48000000,
|
|
@@ -727,20 +676,17 @@ static struct clk mmc2_ck = {
|
|
|
RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
|
|
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
|
|
|
.enable_bit = 20,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk virtual_ck_mpu = {
|
|
|
.name = "mpu",
|
|
|
+ .ops = &clkops_generic,
|
|
|
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
|
|
|
CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
|
|
|
.parent = &arm_ck, /* Is smarter alias for */
|
|
|
.recalc = &followparent_recalc,
|
|
|
.set_rate = &omap1_select_table_rate,
|
|
|
.round_rate = &omap1_round_to_table_rate,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
|
|
@@ -748,23 +694,21 @@ remains active during MPU idle whenever this is enabled */
|
|
|
static struct clk i2c_fck = {
|
|
|
.name = "i2c_fck",
|
|
|
.id = 1,
|
|
|
+ .ops = &clkops_generic,
|
|
|
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
|
|
|
CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED,
|
|
|
.parent = &armxor_ck.clk,
|
|
|
.recalc = &followparent_recalc,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk i2c_ick = {
|
|
|
.name = "i2c_ick",
|
|
|
.id = 1,
|
|
|
+ .ops = &clkops_generic,
|
|
|
.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
|
|
|
ALWAYS_ENABLED,
|
|
|
.parent = &armper_ck.clk,
|
|
|
.recalc = &followparent_recalc,
|
|
|
- .enable = &omap1_clk_enable_generic,
|
|
|
- .disable = &omap1_clk_disable_generic,
|
|
|
};
|
|
|
|
|
|
static struct clk * onchip_clks[] = {
|