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@@ -1139,6 +1139,106 @@ dynamic_cca_tune:
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rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
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}
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+/*
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+ * Queue handlers.
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+ */
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+static void rt61pci_start_queue(struct data_queue *queue)
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+{
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+ struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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+ u32 reg;
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+
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+ switch (queue->qid) {
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+ case QID_RX:
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+ rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
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+ rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
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+ rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
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+ break;
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+ case QID_BEACON:
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+ rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
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+ rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
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+ rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
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+ rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
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+ rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+
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+static void rt61pci_kick_queue(struct data_queue *queue)
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+{
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+ struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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+ u32 reg;
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+
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+ switch (queue->qid) {
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+ case QID_AC_BE:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_AC_BK:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_AC_VI:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_AC_VO:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+
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+static void rt61pci_stop_queue(struct data_queue *queue)
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+{
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+ struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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+ u32 reg;
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+
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+ switch (queue->qid) {
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+ case QID_AC_BE:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_AC_BK:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_AC_VI:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_AC_VO:
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+ rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
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+ rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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+ break;
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+ case QID_RX:
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+ rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
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+ rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1);
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+ rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
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+ break;
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+ case QID_BEACON:
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+ rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
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+ rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
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+ rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
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+ rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
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+ rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+
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/*
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* Firmware functions
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*/
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@@ -1616,17 +1716,6 @@ static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
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/*
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* Device state switch handlers.
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*/
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-static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
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- enum dev_state state)
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-{
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- u32 reg;
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-
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- rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
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- rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
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- (state == STATE_RADIO_RX_OFF));
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- rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
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-}
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-
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static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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enum dev_state state)
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{
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@@ -1744,8 +1833,10 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
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rt61pci_disable_radio(rt2x00dev);
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break;
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case STATE_RADIO_RX_ON:
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+ rt61pci_start_queue(rt2x00dev->rx);
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+ break;
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case STATE_RADIO_RX_OFF:
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- rt61pci_toggle_rx(rt2x00dev, state);
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+ rt61pci_stop_queue(rt2x00dev->rx);
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break;
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case STATE_RADIO_IRQ_ON:
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case STATE_RADIO_IRQ_ON_ISR:
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@@ -1925,41 +2016,6 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
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entry->skb = NULL;
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}
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-static void rt61pci_kick_tx_queue(struct data_queue *queue)
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-{
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- struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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- u32 reg;
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-
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- rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE));
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK));
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI));
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO));
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- rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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-}
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-
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-static void rt61pci_kill_tx_queue(struct data_queue *queue)
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-{
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- struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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- u32 reg;
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-
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- if (queue->qid == QID_BEACON) {
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- rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
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- rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
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- rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
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- rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
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- rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
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- return;
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- }
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-
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- rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE));
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK));
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI));
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO));
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- rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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-}
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-
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/*
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* RX control handlers
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*/
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@@ -2846,8 +2902,8 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
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.link_tuner = rt61pci_link_tuner,
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.write_tx_desc = rt61pci_write_tx_desc,
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.write_beacon = rt61pci_write_beacon,
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- .kick_tx_queue = rt61pci_kick_tx_queue,
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- .kill_tx_queue = rt61pci_kill_tx_queue,
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+ .kick_tx_queue = rt61pci_kick_queue,
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+ .kill_tx_queue = rt61pci_stop_queue,
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.fill_rxdone = rt61pci_fill_rxdone,
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.config_shared_key = rt61pci_config_shared_key,
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.config_pairwise_key = rt61pci_config_pairwise_key,
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