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@@ -5253,6 +5253,78 @@ static s32 e1000_check_downshift(struct e1000_hw *hw)
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return E1000_SUCCESS;
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return E1000_SUCCESS;
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}
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}
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+static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
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+ IGP01E1000_PHY_AGC_PARAM_A,
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+ IGP01E1000_PHY_AGC_PARAM_B,
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+ IGP01E1000_PHY_AGC_PARAM_C,
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+ IGP01E1000_PHY_AGC_PARAM_D
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+};
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+
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+static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
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+{
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+ u16 min_length, max_length;
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+ u16 phy_data, i;
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+ s32 ret_val;
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+
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+ ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
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+ if (ret_val)
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+ return ret_val;
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+
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+ if (hw->dsp_config_state != e1000_dsp_config_enabled)
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+ return 0;
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+
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+ if (min_length >= e1000_igp_cable_length_50) {
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+ for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
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+ ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
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+ &phy_data);
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+ if (ret_val)
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+ return ret_val;
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+
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+ phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
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+
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+ ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
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+ phy_data);
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+ if (ret_val)
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+ return ret_val;
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+ }
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+ hw->dsp_config_state = e1000_dsp_config_activated;
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+ } else {
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+ u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
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+ u32 idle_errs = 0;
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+
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+ /* clear previous idle error counts */
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+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
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+ if (ret_val)
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+ return ret_val;
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+
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+ for (i = 0; i < ffe_idle_err_timeout; i++) {
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+ udelay(1000);
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+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
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+ &phy_data);
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+ if (ret_val)
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+ return ret_val;
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+
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+ idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
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+ if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
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+ hw->ffe_config_state = e1000_ffe_config_active;
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+
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+ ret_val = e1000_write_phy_reg(hw,
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+ IGP01E1000_PHY_DSP_FFE,
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+ IGP01E1000_PHY_DSP_FFE_CM_CP);
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+ if (ret_val)
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+ return ret_val;
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+ break;
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+ }
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+
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+ if (idle_errs)
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+ ffe_idle_err_timeout =
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+ FFE_IDLE_ERR_COUNT_TIMEOUT_100;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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/**
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/**
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* e1000_config_dsp_after_link_change
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* e1000_config_dsp_after_link_change
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* @hw: Struct containing variables accessed by shared code
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* @hw: Struct containing variables accessed by shared code
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@@ -5269,13 +5341,6 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
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{
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{
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s32 ret_val;
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s32 ret_val;
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u16 phy_data, phy_saved_data, speed, duplex, i;
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u16 phy_data, phy_saved_data, speed, duplex, i;
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- static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
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- IGP01E1000_PHY_AGC_PARAM_A,
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- IGP01E1000_PHY_AGC_PARAM_B,
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- IGP01E1000_PHY_AGC_PARAM_C,
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- IGP01E1000_PHY_AGC_PARAM_D
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- };
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- u16 min_length, max_length;
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e_dbg("e1000_config_dsp_after_link_change");
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e_dbg("e1000_config_dsp_after_link_change");
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@@ -5290,84 +5355,9 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
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}
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}
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if (speed == SPEED_1000) {
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if (speed == SPEED_1000) {
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-
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- ret_val =
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- e1000_get_cable_length(hw, &min_length,
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- &max_length);
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+ ret_val = e1000_1000Mb_check_cable_length(hw);
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if (ret_val)
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if (ret_val)
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return ret_val;
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return ret_val;
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-
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- if ((hw->dsp_config_state == e1000_dsp_config_enabled)
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- && min_length >= e1000_igp_cable_length_50) {
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-
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- for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
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- ret_val =
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- e1000_read_phy_reg(hw,
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- dsp_reg_array[i],
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- &phy_data);
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- if (ret_val)
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- return ret_val;
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-
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- phy_data &=
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- ~IGP01E1000_PHY_EDAC_MU_INDEX;
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-
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- ret_val =
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- e1000_write_phy_reg(hw,
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- dsp_reg_array
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- [i], phy_data);
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- if (ret_val)
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- return ret_val;
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- }
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- hw->dsp_config_state =
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- e1000_dsp_config_activated;
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- }
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-
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- if ((hw->ffe_config_state == e1000_ffe_config_enabled)
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- && (min_length < e1000_igp_cable_length_50)) {
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-
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- u16 ffe_idle_err_timeout =
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- FFE_IDLE_ERR_COUNT_TIMEOUT_20;
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- u32 idle_errs = 0;
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-
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- /* clear previous idle error counts */
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- ret_val =
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- e1000_read_phy_reg(hw, PHY_1000T_STATUS,
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- &phy_data);
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- if (ret_val)
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- return ret_val;
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-
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- for (i = 0; i < ffe_idle_err_timeout; i++) {
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- udelay(1000);
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- ret_val =
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- e1000_read_phy_reg(hw,
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- PHY_1000T_STATUS,
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- &phy_data);
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- if (ret_val)
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- return ret_val;
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-
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- idle_errs +=
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- (phy_data &
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- SR_1000T_IDLE_ERROR_CNT);
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- if (idle_errs >
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- SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
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- {
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- hw->ffe_config_state =
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- e1000_ffe_config_active;
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-
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- ret_val =
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- e1000_write_phy_reg(hw,
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- IGP01E1000_PHY_DSP_FFE,
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- IGP01E1000_PHY_DSP_FFE_CM_CP);
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- if (ret_val)
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- return ret_val;
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- break;
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- }
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-
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- if (idle_errs)
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- ffe_idle_err_timeout =
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- FFE_IDLE_ERR_COUNT_TIMEOUT_100;
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- }
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- }
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}
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}
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} else {
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} else {
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if (hw->dsp_config_state == e1000_dsp_config_activated) {
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if (hw->dsp_config_state == e1000_dsp_config_activated) {
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