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@@ -59,49 +59,49 @@
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#define IRQ_ADCPARENT S3C2410_IRQ(31)
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/* interrupts generated from the external interrupts sources */
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-#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
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-#define IRQ_EINT5 S3C2410_IRQ(33)
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-#define IRQ_EINT6 S3C2410_IRQ(34)
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-#define IRQ_EINT7 S3C2410_IRQ(35)
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-#define IRQ_EINT8 S3C2410_IRQ(36)
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-#define IRQ_EINT9 S3C2410_IRQ(37)
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-#define IRQ_EINT10 S3C2410_IRQ(38)
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-#define IRQ_EINT11 S3C2410_IRQ(39)
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-#define IRQ_EINT12 S3C2410_IRQ(40)
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-#define IRQ_EINT13 S3C2410_IRQ(41)
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-#define IRQ_EINT14 S3C2410_IRQ(42)
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-#define IRQ_EINT15 S3C2410_IRQ(43)
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-#define IRQ_EINT16 S3C2410_IRQ(44)
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-#define IRQ_EINT17 S3C2410_IRQ(45)
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-#define IRQ_EINT18 S3C2410_IRQ(46)
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-#define IRQ_EINT19 S3C2410_IRQ(47)
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-#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
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-#define IRQ_EINT21 S3C2410_IRQ(49)
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-#define IRQ_EINT22 S3C2410_IRQ(50)
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-#define IRQ_EINT23 S3C2410_IRQ(51)
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+#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
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+#define IRQ_EINT5 S3C2410_IRQ(37)
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+#define IRQ_EINT6 S3C2410_IRQ(38)
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+#define IRQ_EINT7 S3C2410_IRQ(39)
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+#define IRQ_EINT8 S3C2410_IRQ(40)
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+#define IRQ_EINT9 S3C2410_IRQ(41)
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+#define IRQ_EINT10 S3C2410_IRQ(42)
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+#define IRQ_EINT11 S3C2410_IRQ(43)
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+#define IRQ_EINT12 S3C2410_IRQ(44)
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+#define IRQ_EINT13 S3C2410_IRQ(45)
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+#define IRQ_EINT14 S3C2410_IRQ(46)
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+#define IRQ_EINT15 S3C2410_IRQ(47)
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+#define IRQ_EINT16 S3C2410_IRQ(48)
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+#define IRQ_EINT17 S3C2410_IRQ(49)
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+#define IRQ_EINT18 S3C2410_IRQ(50)
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+#define IRQ_EINT19 S3C2410_IRQ(51)
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+#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
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+#define IRQ_EINT21 S3C2410_IRQ(53)
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+#define IRQ_EINT22 S3C2410_IRQ(54)
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+#define IRQ_EINT23 S3C2410_IRQ(55)
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#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
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#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
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-#define IRQ_LCD_FIFO S3C2410_IRQ(52)
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-#define IRQ_LCD_FRAME S3C2410_IRQ(53)
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+#define IRQ_LCD_FIFO S3C2410_IRQ(56)
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+#define IRQ_LCD_FRAME S3C2410_IRQ(57)
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/* IRQs for the interal UARTs, and ADC
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* these need to be ordered in number of appearance in the
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* SUBSRC mask register
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*/
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-#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54)
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+#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
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-#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */
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+#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
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#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
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#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
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-#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */
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+#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
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#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
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#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
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-#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */
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+#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
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#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
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#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
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@@ -136,7 +136,7 @@
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/* second interrupt-register of s3c2416/s3c2450 */
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-#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29)
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+#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
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#define IRQ_S3C2416_2D S3C2416_IRQ(0)
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#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
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#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
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