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@@ -3948,48 +3948,6 @@ static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
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return rc;
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return rc;
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}
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}
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-static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
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- struct bnx2x_phy *phy)
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-{
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- u16 val;
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- bnx2x_cl45_read(bp, phy,
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- MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
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-
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- if (val == 0) {
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- /* Mustn't set low power mode in 8073 A0 */
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- return;
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- }
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-
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- /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
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- bnx2x_cl45_read(bp, phy,
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- MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
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- val &= ~(1<<13);
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- bnx2x_cl45_write(bp, phy,
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- MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
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-
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- /* PLL controls */
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
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-
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- /* Tx Controls */
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
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-
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- /* Rx Controls */
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
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-
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- /* Enable PLL sequencer (use read-modify-write to set bit 13) */
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- bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
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- val |= (1<<13);
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- bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
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-}
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-
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/******************************************************************/
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/******************************************************************/
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/* BCM8073 PHY SECTION */
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/* BCM8073 PHY SECTION */
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/******************************************************************/
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/******************************************************************/
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@@ -4148,8 +4106,6 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
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bnx2x_8073_set_pause_cl37(params, phy, vars);
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bnx2x_8073_set_pause_cl37(params, phy, vars);
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- bnx2x_8073_set_xaui_low_power_mode(bp, phy);
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-
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bnx2x_cl45_read(bp, phy,
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bnx2x_cl45_read(bp, phy,
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MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
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MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
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@@ -6519,6 +6475,18 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
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MDIO_PMA_DEVAD,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_8481_LED1_MASK,
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MDIO_PMA_REG_8481_LED1_MASK,
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0x80);
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0x80);
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+
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+ /* Tell LED3 to blink on source */
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+ bnx2x_cl45_read(bp, phy,
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+ MDIO_PMA_DEVAD,
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+ MDIO_PMA_REG_8481_LINK_SIGNAL,
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+ &val);
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+ val &= ~(7<<6);
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+ val |= (1<<6); /* A83B[8:6]= 1 */
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+ bnx2x_cl45_write(bp, phy,
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+ MDIO_PMA_DEVAD,
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+ MDIO_PMA_REG_8481_LINK_SIGNAL,
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+ val);
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}
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}
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break;
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break;
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}
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}
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@@ -7720,10 +7688,13 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
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struct bnx2x_phy phy[PORT_MAX];
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struct bnx2x_phy phy[PORT_MAX];
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struct bnx2x_phy *phy_blk[PORT_MAX];
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struct bnx2x_phy *phy_blk[PORT_MAX];
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u16 val;
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u16 val;
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- s8 port;
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+ s8 port = 0;
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s8 port_of_path = 0;
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s8 port_of_path = 0;
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-
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- bnx2x_ext_phy_hw_reset(bp, 0);
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+ u32 swap_val, swap_override;
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+ swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
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+ swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
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+ port ^= (swap_val && swap_override);
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+ bnx2x_ext_phy_hw_reset(bp, port);
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/* PART1 - Reset both phys */
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/* PART1 - Reset both phys */
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for (port = PORT_MAX - 1; port >= PORT_0; port--) {
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for (port = PORT_MAX - 1; port >= PORT_0; port--) {
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u32 shmem_base, shmem2_base;
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u32 shmem_base, shmem2_base;
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