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[PATCH] PCI: i386/x86_84: disable PCI resource decode on device disable

When a PCI device is disabled via pci_disable_device(), it's still
left decoding its BAR resource ranges even though its driver
will have likely released those regions (and may even have
unloaded). pci_enable_device() already explicitly enables
BAR resource decode for the device being enabled. This patch
disables resource decode for the PCI device being disabled,
making it symmetric with the enable call.

I saw this while doing something else, not because of a
problem report. Still, seems to be the correct thing to do.

Signed-off-by: Rajesh Shah <rajesh.shah@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Rajesh Shah 19 years ago
parent
commit
53e4d30dd6
3 changed files with 11 additions and 0 deletions
  1. 1 0
      arch/i386/pci/common.c
  2. 9 0
      arch/i386/pci/i386.c
  3. 1 0
      arch/i386/pci/pci.h

+ 1 - 0
arch/i386/pci/common.c

@@ -288,6 +288,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
 
 void pcibios_disable_device (struct pci_dev *dev)
 {
+	pcibios_disable_resources(dev);
 	if (pcibios_disable_irq)
 		pcibios_disable_irq(dev);
 }

+ 9 - 0
arch/i386/pci/i386.c

@@ -242,6 +242,15 @@ int pcibios_enable_resources(struct pci_dev *dev, int mask)
 	return 0;
 }
 
+void pcibios_disable_resources(struct pci_dev *dev)
+{
+	u16 cmd;
+
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+	pci_write_config_word(dev, PCI_COMMAND, cmd);
+}
+
 /*
  *  If we set up a device for bus mastering, we need to check the latency
  *  timer as certain crappy BIOSes forget to set it properly.

+ 1 - 0
arch/i386/pci/pci.h

@@ -35,6 +35,7 @@ extern unsigned int pcibios_max_latency;
 
 void pcibios_resource_survey(void);
 int pcibios_enable_resources(struct pci_dev *, int);
+void pcibios_disable_resources(struct pci_dev *);
 
 /* pci-pc.c */