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@@ -112,12 +112,34 @@ static void pmc_sys_mode(struct clk *clk, int is_on)
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at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
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}
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+static void pmc_uckr_mode(struct clk *clk, int is_on)
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+{
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+ unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
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+
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+ if (is_on) {
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+ is_on = AT91_PMC_LOCKU;
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+ at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
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+ } else
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+ at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
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+
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+ do {
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+ cpu_relax();
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+ } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
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+}
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+
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/* USB function clocks (PLLB must be 48 MHz) */
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static struct clk udpck = {
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.name = "udpck",
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.parent = &pllb,
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.mode = pmc_sys_mode,
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};
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+static struct clk utmi_clk = {
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+ .name = "utmi_clk",
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+ .parent = &main_clk,
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+ .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
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+ .mode = pmc_uckr_mode,
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+ .type = CLK_TYPE_PLL,
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+};
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static struct clk uhpck = {
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.name = "uhpck",
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.parent = &pllb,
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@@ -361,7 +383,7 @@ static void __init init_programmable_clock(struct clk *clk)
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static int at91_clk_show(struct seq_file *s, void *unused)
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{
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- u32 scsr, pcsr, sr;
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+ u32 scsr, pcsr, uckr = 0, sr;
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struct clk *clk;
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seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
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@@ -370,6 +392,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
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seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
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seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
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seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
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+ if (cpu_is_at91cap9())
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+ seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
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seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
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seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
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@@ -382,6 +406,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
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state = (scsr & clk->pmc_mask) ? "on" : "off";
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else if (clk->mode == pmc_periph_mode)
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state = (pcsr & clk->pmc_mask) ? "on" : "off";
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+ else if (clk->mode == pmc_uckr_mode)
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+ state = (uckr & clk->pmc_mask) ? "on" : "off";
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else if (clk->pmc_mask)
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state = (sr & clk->pmc_mask) ? "on" : "off";
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else if (clk == &clk32k || clk == &main_clk)
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@@ -581,6 +607,17 @@ int __init at91_clock_init(unsigned long main_clock)
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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+ /*
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+ * USB HS clock init
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+ */
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+ if (cpu_is_at91cap9()) {
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+ /*
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+ * multiplier is hard-wired to 40
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+ * (obtain the USB High Speed 480 MHz when input is 12 MHz)
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+ */
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+ utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
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+ }
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+
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/*
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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@@ -598,6 +635,9 @@ int __init at91_clock_init(unsigned long main_clock)
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for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
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list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
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+ if (cpu_is_at91cap9())
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+ list_add_tail(&utmi_clk.node, &clocks);
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+
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/* MCK and CPU clock are "always on" */
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clk_enable(&mck);
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