|
@@ -56,7 +56,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
|
|
|
if (irq < 0)
|
|
|
return irq;
|
|
|
|
|
|
- set_irq_msi(irq, desc);
|
|
|
+ irq_set_msi_desc(irq, desc);
|
|
|
cpus_and(mask, irq_to_domain(irq), cpu_online_map);
|
|
|
dest_phys_id = cpu_physical_id(first_cpu(mask));
|
|
|
vector = irq_to_vector(irq);
|
|
@@ -75,7 +75,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
|
|
|
MSI_DATA_VECTOR(vector);
|
|
|
|
|
|
write_msi_msg(irq, &msg);
|
|
|
- set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
|
|
|
+ irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
@@ -206,8 +206,8 @@ int arch_setup_dmar_msi(unsigned int irq)
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
dmar_msi_write(irq, &msg);
|
|
|
- set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
|
|
|
- "edge");
|
|
|
+ irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
|
|
|
+ "edge");
|
|
|
return 0;
|
|
|
}
|
|
|
#endif /* CONFIG_DMAR */
|