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@@ -1018,10 +1018,19 @@ static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
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hdmi_non_intrinsic_event(codec, res);
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}
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-static void haswell_verify_pin_D0(struct hda_codec *codec, hda_nid_t nid)
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+static void haswell_verify_pin_D0(struct hda_codec *codec,
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+ hda_nid_t cvt_nid, hda_nid_t nid)
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{
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int pwr, lamp, ramp;
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+ /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
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+ * thus pins could only choose converter 0 for use. Make sure the
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+ * converters are in correct power state */
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+ pwr = snd_hda_codec_read(codec, cvt_nid, 0, AC_VERB_GET_POWER_STATE, 0);
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+ pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
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+ if (pwr != AC_PWRST_D0)
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+ snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
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+
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pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
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pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
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if (pwr != AC_PWRST_D0) {
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@@ -1068,7 +1077,7 @@ static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
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int new_pinctl = 0;
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if (codec->vendor_id == 0x80862807)
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- haswell_verify_pin_D0(codec, pin_nid);
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+ haswell_verify_pin_D0(codec, cvt_nid, pin_nid);
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if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
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pinctl = snd_hda_codec_read(codec, pin_nid, 0,
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