|
@@ -31,8 +31,7 @@ struct amba_device uart_device[] = {
|
|
},
|
|
},
|
|
.res = {
|
|
.res = {
|
|
.start = SPEAR6XX_ICM1_UART0_BASE,
|
|
.start = SPEAR6XX_ICM1_UART0_BASE,
|
|
- .end = SPEAR6XX_ICM1_UART0_BASE +
|
|
|
|
- SPEAR6XX_ICM1_UART0_SIZE - 1,
|
|
|
|
|
|
+ .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
},
|
|
.irq = {IRQ_UART_0, NO_IRQ},
|
|
.irq = {IRQ_UART_0, NO_IRQ},
|
|
@@ -42,8 +41,7 @@ struct amba_device uart_device[] = {
|
|
},
|
|
},
|
|
.res = {
|
|
.res = {
|
|
.start = SPEAR6XX_ICM1_UART1_BASE,
|
|
.start = SPEAR6XX_ICM1_UART1_BASE,
|
|
- .end = SPEAR6XX_ICM1_UART1_BASE +
|
|
|
|
- SPEAR6XX_ICM1_UART1_SIZE - 1,
|
|
|
|
|
|
+ .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
},
|
|
.irq = {IRQ_UART_1, NO_IRQ},
|
|
.irq = {IRQ_UART_1, NO_IRQ},
|
|
@@ -72,8 +70,7 @@ struct amba_device gpio_device[] = {
|
|
},
|
|
},
|
|
.res = {
|
|
.res = {
|
|
.start = SPEAR6XX_CPU_GPIO_BASE,
|
|
.start = SPEAR6XX_CPU_GPIO_BASE,
|
|
- .end = SPEAR6XX_CPU_GPIO_BASE +
|
|
|
|
- SPEAR6XX_CPU_GPIO_SIZE - 1,
|
|
|
|
|
|
+ .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
},
|
|
.irq = {IRQ_LOCAL_GPIO, NO_IRQ},
|
|
.irq = {IRQ_LOCAL_GPIO, NO_IRQ},
|
|
@@ -84,8 +81,7 @@ struct amba_device gpio_device[] = {
|
|
},
|
|
},
|
|
.res = {
|
|
.res = {
|
|
.start = SPEAR6XX_ICM3_GPIO_BASE,
|
|
.start = SPEAR6XX_ICM3_GPIO_BASE,
|
|
- .end = SPEAR6XX_ICM3_GPIO_BASE +
|
|
|
|
- SPEAR6XX_ICM3_GPIO_SIZE - 1,
|
|
|
|
|
|
+ .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
},
|
|
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
|
|
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
|
|
@@ -96,8 +92,7 @@ struct amba_device gpio_device[] = {
|
|
},
|
|
},
|
|
.res = {
|
|
.res = {
|
|
.start = SPEAR6XX_ICM2_GPIO_BASE,
|
|
.start = SPEAR6XX_ICM2_GPIO_BASE,
|
|
- .end = SPEAR6XX_ICM2_GPIO_BASE +
|
|
|
|
- SPEAR6XX_ICM2_GPIO_SIZE - 1,
|
|
|
|
|
|
+ .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
},
|
|
.irq = {IRQ_APPL_GPIO, NO_IRQ},
|
|
.irq = {IRQ_APPL_GPIO, NO_IRQ},
|
|
@@ -122,27 +117,27 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
|
|
{
|
|
{
|
|
.virtual = VA_SPEAR6XX_ICM1_UART0_BASE,
|
|
.virtual = VA_SPEAR6XX_ICM1_UART0_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
|
|
- .length = SPEAR6XX_ICM1_UART0_SIZE,
|
|
|
|
|
|
+ .length = SZ_4K,
|
|
.type = MT_DEVICE
|
|
.type = MT_DEVICE
|
|
}, {
|
|
}, {
|
|
.virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
|
|
.virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
|
|
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
|
|
- .length = SPEAR6XX_CPU_VIC_PRI_SIZE,
|
|
|
|
|
|
+ .length = SZ_4K,
|
|
.type = MT_DEVICE
|
|
.type = MT_DEVICE
|
|
}, {
|
|
}, {
|
|
.virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
|
|
.virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
|
|
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
|
|
- .length = SPEAR6XX_CPU_VIC_SEC_SIZE,
|
|
|
|
|
|
+ .length = SZ_4K,
|
|
.type = MT_DEVICE
|
|
.type = MT_DEVICE
|
|
}, {
|
|
}, {
|
|
.virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
|
|
.virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
|
|
- .length = SPEAR6XX_ICM3_MISC_REG_BASE,
|
|
|
|
|
|
+ .length = SZ_4K,
|
|
.type = MT_DEVICE
|
|
.type = MT_DEVICE
|
|
}, {
|
|
}, {
|
|
.virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
|
|
.virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
|
|
- .length = SPEAR6XX_ICM3_MISC_REG_SIZE,
|
|
|
|
|
|
+ .length = SZ_4K,
|
|
.type = MT_DEVICE
|
|
.type = MT_DEVICE
|
|
},
|
|
},
|
|
};
|
|
};
|