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@@ -67,6 +67,26 @@ static struct irq_chip pxa_internal_chip_low = {
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.set_wake = pxa_set_wake,
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};
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+void __init pxa_init_irq_low(void)
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+{
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+ int irq;
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+
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+ /* disable all IRQs */
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+ ICMR = 0;
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+
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+ /* all IRQs are IRQ, not FIQ */
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+ ICLR = 0;
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+
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+ /* only unmasked interrupts kick us out of idle */
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+ ICCR = 1;
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+
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+ for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
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+ set_irq_chip(irq, &pxa_internal_chip_low);
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+ set_irq_handler(irq, handle_level_irq);
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+ set_irq_flags(irq, IRQF_VALID);
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+ }
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+}
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+
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#ifdef CONFIG_PXA27x
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/*
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@@ -331,12 +351,6 @@ void __init pxa_init_irq(void)
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{
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int irq;
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- /* disable all IRQs */
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- ICMR = 0;
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-
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- /* all IRQs are IRQ, not FIQ */
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- ICLR = 0;
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-
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/* clear all GPIO edge detects */
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GFER0 = 0;
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GFER1 = 0;
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@@ -355,18 +369,10 @@ void __init pxa_init_irq(void)
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GEDR3 = GEDR3;
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#endif
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- /* only unmasked interrupts kick us out of idle */
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- ICCR = 1;
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-
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/* GPIO 0 and 1 must have their mask bit always set */
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GPIO_IRQ_mask[0] = 3;
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- for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
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- set_irq_chip(irq, &pxa_internal_chip_low);
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- set_irq_handler(irq, handle_level_irq);
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- set_irq_flags(irq, IRQF_VALID);
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- }
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-
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+ pxa_init_irq_low();
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#ifdef CONFIG_PXA27x
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pxa_init_irq_high();
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#endif
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