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@@ -0,0 +1,493 @@
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+/*
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+ * Intel 3000/3010 Memory Controller kernel module
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+ * Copyright (C) 2007 Akamai Technologies, Inc.
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+ * Shamelessly copied from:
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+ * Intel D82875P Memory Controller kernel module
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+ * (C) 2003 Linux Networx (http://lnxi.com)
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+ *
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+ * This file may be distributed under the terms of the
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+ * GNU General Public License.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/pci.h>
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+#include <linux/pci_ids.h>
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+#include <linux/slab.h>
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+#include "edac_core.h"
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+
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+#define I3000_REVISION "1.1"
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+
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+#define EDAC_MOD_STR "i3000_edac"
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+
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+#define I3000_RANKS 8
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+#define I3000_RANKS_PER_CHANNEL 4
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+#define I3000_CHANNELS 2
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+
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+/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
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+
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+#define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
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+#define I3000_MCHBAR_MASK 0xffffc000
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+#define I3000_MMR_WINDOW_SIZE 16384
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+
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+#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
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+ *
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+ * 7:1 reserved
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+ * 0 bit 32 of address
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+ */
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+#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
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+ *
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+ * 31:7 address
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+ * 6:1 reserved
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+ * 0 Error channel 0/1
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+ */
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+#define I3000_DEAP_GRAIN (1 << 7)
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+#define I3000_DEAP_PFN(edeap, deap) ((((edeap) & 1) << (32 - PAGE_SHIFT)) | \
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+ ((deap) >> PAGE_SHIFT))
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+#define I3000_DEAP_OFFSET(deap) ((deap) & ~(I3000_DEAP_GRAIN-1) & ~PAGE_MASK)
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+#define I3000_DEAP_CHANNEL(deap) ((deap) & 1)
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+
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+#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
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+ *
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+ * 7:0 DRAM ECC Syndrome
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+ */
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+
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+#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
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+ *
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+ * 15:12 reserved
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+ * 11 MCH Thermal Sensor Event for SMI/SCI/SERR
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+ * 10 reserved
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+ * 9 LOCK to non-DRAM Memory Flag (LCKF)
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+ * 8 Received Refresh Timeout Flag (RRTOF)
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+ * 7:2 reserved
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+ * 1 Multiple-bit DRAM ECC Error Flag (DMERR)
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+ * 0 Single-bit DRAM ECC Error Flag (DSERR)
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+ */
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+#define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
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+#define I3000_ERRSTS_UE 0x0002
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+#define I3000_ERRSTS_CE 0x0001
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+
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+#define I3000_ERRCMD 0xca /* Error Command (16b)
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+ *
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+ * 15:12 reserved
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+ * 11 SERR on MCH Thermal Sensor Event (TSESERR)
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+ * 10 reserved
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+ * 9 SERR on LOCK to non-DRAM Memory (LCKERR)
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+ * 8 SERR on DRAM Refresh Timeout (DRTOERR)
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+ * 7:2 reserved
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+ * 1 SERR Multiple-Bit DRAM ECC Error (DMERR)
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+ * 0 SERR on Single-Bit ECC Error (DSERR)
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+ */
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+
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+/* Intel MMIO register space - device 0 function 0 - MMR space */
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+
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+#define I3000_DRB_SHIFT 25 /* 32MiB grain */
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+
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+#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
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+ *
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+ * 7:0 Channel 0 DRAM Rank Boundary Address
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+ */
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+#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
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+ *
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+ * 7:0 Channel 1 DRAM Rank Boundary Address
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+ */
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+
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+#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
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+ *
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+ * 7 reserved
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+ * 6:4 DRAM odd Rank Attribute
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+ * 3 reserved
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+ * 2:0 DRAM even Rank Attribute
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+ *
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+ * Each attribute defines the page
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+ * size of the corresponding rank:
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+ * 000: unpopulated
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+ * 001: reserved
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+ * 010: 4 KB
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+ * 011: 8 KB
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+ * 100: 16 KB
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+ * Others: reserved
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+ */
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+#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
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+#define ODD_RANK_ATTRIB(dra) (((dra) & 0x70) >> 4)
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+#define EVEN_RANK_ATTRIB(dra) ((dra) & 0x07)
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+
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+#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
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+ *
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+ * 31:30 reserved
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+ * 29 Initialization Complete (IC)
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+ * 28:11 reserved
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+ * 10:8 Refresh Mode Select (RMS)
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+ * 7 reserved
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+ * 6:4 Mode Select (SMS)
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+ * 3:2 reserved
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+ * 1:0 DRAM Type (DT)
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+ */
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+
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+#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
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+ *
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+ * 31 Enhanced Addressing Enable (ENHADE)
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+ * 30:0 reserved
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+ */
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+
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+
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+enum i3000p_chips {
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+ I3000 = 0,
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+};
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+
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+struct i3000_dev_info {
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+ const char *ctl_name;
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+};
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+
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+struct i3000_error_info {
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+ u16 errsts;
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+ u8 derrsyn;
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+ u8 edeap;
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+ u32 deap;
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+ u16 errsts2;
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+};
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+
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+static const struct i3000_dev_info i3000_devs[] = {
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+ [I3000] = {
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+ .ctl_name = "i3000"
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+ },
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+};
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+
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+static struct pci_dev *mci_pdev = NULL;
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+static int i3000_registered = 1;
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+
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+static void i3000_get_error_info(struct mem_ctl_info *mci,
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+ struct i3000_error_info *info)
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+{
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+ struct pci_dev *pdev;
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+
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+ pdev = to_pci_dev(mci->dev);
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+
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+ /*
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+ * This is a mess because there is no atomic way to read all the
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+ * registers at once and the registers can transition from CE being
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+ * overwritten by UE.
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+ */
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+ pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
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+ if (!(info->errsts & I3000_ERRSTS_BITS))
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+ return;
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+ pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
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+ pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
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+ pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
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+ pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
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+
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+ /*
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+ * If the error is the same for both reads then the first set
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+ * of reads is valid. If there is a change then there is a CE
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+ * with no info and the second set of reads is valid and
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+ * should be UE info.
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+ */
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+ if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
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+ pci_read_config_byte(pdev, I3000_EDEAP,
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+ &info->edeap);
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+ pci_read_config_dword(pdev, I3000_DEAP,
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+ &info->deap);
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+ pci_read_config_byte(pdev, I3000_DERRSYN,
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+ &info->derrsyn);
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+ }
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+
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+ /* Clear any error bits.
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+ * (Yes, we really clear bits by writing 1 to them.)
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+ */
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+ pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, I3000_ERRSTS_BITS);
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+}
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+
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+static int i3000_process_error_info(struct mem_ctl_info *mci,
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+ struct i3000_error_info *info, int handle_errors)
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+{
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+ int row, multi_chan;
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+ int pfn, offset, channel;
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+
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+ multi_chan = mci->csrows[0].nr_channels - 1;
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+
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+ if (!(info->errsts & I3000_ERRSTS_BITS))
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+ return 0;
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+
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+ if (!handle_errors)
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+ return 1;
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+
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+ if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
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+ edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
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+ info->errsts = info->errsts2;
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+ }
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+
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+ pfn = I3000_DEAP_PFN(info->edeap, info->deap);
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+ offset = I3000_DEAP_OFFSET(info->deap);
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+ channel = I3000_DEAP_CHANNEL(info->deap);
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+
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+ row = edac_mc_find_csrow_by_page(mci, pfn);
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+
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+ if (info->errsts & I3000_ERRSTS_UE)
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+ edac_mc_handle_ue(mci, pfn, offset, row, "i3000 UE");
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+ else
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+ edac_mc_handle_ce(mci, pfn, offset, info->derrsyn, row,
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+ multi_chan ? channel : 0,
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+ "i3000 CE");
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+
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+ return 1;
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+}
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+
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+static void i3000_check(struct mem_ctl_info *mci)
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+{
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+ struct i3000_error_info info;
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+
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+ debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
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+ i3000_get_error_info(mci, &info);
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+ i3000_process_error_info(mci, &info, 1);
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+}
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+
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+static int i3000_is_interleaved(const unsigned char *c0dra,
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+ const unsigned char *c1dra,
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+ const unsigned char *c0drb,
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+ const unsigned char *c1drb)
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+{
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+ int i;
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+
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+ /* If the channels aren't populated identically then
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+ * we're not interleaved.
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+ */
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+ for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
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+ if (ODD_RANK_ATTRIB(c0dra[i]) != ODD_RANK_ATTRIB(c1dra[i]) ||
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+ EVEN_RANK_ATTRIB(c0dra[i]) != EVEN_RANK_ATTRIB(c1dra[i]))
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+ return 0;
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+
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+ /* If the rank boundaries for the two channels are different
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+ * then we're not interleaved.
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+ */
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+ for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
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+ if (c0drb[i] != c1drb[i])
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+ return 0;
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+
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+ return 1;
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+}
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+
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+static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
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+{
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+ int rc;
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+ int i;
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+ struct mem_ctl_info *mci = NULL;
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+ unsigned long last_cumul_size;
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+ int interleaved, nr_channels;
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+ unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
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+ unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
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+ unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
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+ unsigned long mchbar;
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+ void *window;
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+
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+ debugf0("MC: %s()\n", __func__);
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+
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+ pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *)&mchbar);
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+ mchbar &= I3000_MCHBAR_MASK;
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+ window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
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+ if (!window) {
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+ printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n", mchbar);
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+ return -ENODEV;
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+ }
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+
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+ c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
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+ c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
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+ c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
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+ c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
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+
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+ for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
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+ c0drb[i] = readb(window + I3000_C0DRB + i);
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+ c1drb[i] = readb(window + I3000_C1DRB + i);
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+ }
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+
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+ iounmap(window);
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+
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+ /* Figure out how many channels we have.
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+ *
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+ * If we have what the datasheet calls "asymmetric channels"
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+ * (essentially the same as what was called "virtual single
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+ * channel mode" in the i82875) then it's a single channel as
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+ * far as EDAC is concerned.
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+ */
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+ interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
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+ nr_channels = interleaved ? 2 : 1;
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+ mci = edac_mc_alloc(0, I3000_RANKS / nr_channels, nr_channels);
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+ if (!mci)
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+ return -ENOMEM;
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+
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+ debugf3("MC: %s(): init mci\n", __func__);
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+
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+ mci->dev = &pdev->dev;
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+ mci->mtype_cap = MEM_FLAG_DDR2;
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+
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+ mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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+ mci->edac_cap = EDAC_FLAG_SECDED;
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+
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+ mci->mod_name = EDAC_MOD_STR;
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+ mci->mod_ver = I3000_REVISION;
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+ mci->ctl_name = i3000_devs[dev_idx].ctl_name;
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+ mci->dev_name = pci_name(pdev);
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+ mci->edac_check = i3000_check;
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+ mci->ctl_page_to_phys = NULL;
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+
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+ /*
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+ * The dram rank boundary (DRB) reg values are boundary addresses
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+ * for each DRAM rank with a granularity of 32MB. DRB regs are
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+ * cumulative; the last one will contain the total memory
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+ * contained in all ranks.
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+ *
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+ * If we're in interleaved mode then we're only walking through
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+ * the ranks of controller 0, so we double all the values we see.
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+ */
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+ for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
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+ u8 value;
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+ u32 cumul_size;
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+ struct csrow_info *csrow = &mci->csrows[i];
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+
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+ value = drb[i];
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+ cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
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+ if (interleaved)
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+ cumul_size <<= 1;
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+ debugf3("MC: %s(): (%d) cumul_size 0x%x\n",
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+ __func__, i, cumul_size);
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+ if (cumul_size == last_cumul_size) {
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+ csrow->mtype = MEM_EMPTY;
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+ continue;
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+ }
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+
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+ csrow->first_page = last_cumul_size;
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+ csrow->last_page = cumul_size - 1;
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+ csrow->nr_pages = cumul_size - last_cumul_size;
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+ last_cumul_size = cumul_size;
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+ csrow->grain = I3000_DEAP_GRAIN;
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+ csrow->mtype = MEM_DDR2;
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+ csrow->dtype = DEV_UNKNOWN;
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+ csrow->edac_mode = EDAC_UNKNOWN;
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+ }
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+
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+ /* Clear any error bits.
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+ * (Yes, we really clear bits by writing 1 to them.)
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+ */
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+ pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, I3000_ERRSTS_BITS);
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+
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+ rc = -ENODEV;
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+ if (edac_mc_add_mc(mci, 0)) {
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+ debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
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+ goto fail;
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+ }
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+
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+ /* get this far and it's successful */
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+ debugf3("MC: %s(): success\n", __func__);
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+ return 0;
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+
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+ fail:
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+ if (mci)
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+ edac_mc_free(mci);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+/* returns count (>= 0), or negative on error */
|
|
|
+static int __devinit i3000_init_one(struct pci_dev *pdev,
|
|
|
+ const struct pci_device_id *ent)
|
|
|
+{
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ debugf0("MC: %s()\n", __func__);
|
|
|
+
|
|
|
+ if (pci_enable_device(pdev) < 0)
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ rc = i3000_probe1(pdev, ent->driver_data);
|
|
|
+ if (mci_pdev == NULL)
|
|
|
+ mci_pdev = pci_dev_get(pdev);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+static void __devexit i3000_remove_one(struct pci_dev *pdev)
|
|
|
+{
|
|
|
+ struct mem_ctl_info *mci;
|
|
|
+
|
|
|
+ debugf0("%s()\n", __func__);
|
|
|
+
|
|
|
+ if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
|
|
|
+ return;
|
|
|
+
|
|
|
+ edac_mc_free(mci);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct pci_device_id i3000_pci_tbl[] __devinitdata = {
|
|
|
+ {
|
|
|
+ PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
|
|
+ I3000
|
|
|
+ },
|
|
|
+ {
|
|
|
+ 0,
|
|
|
+ } /* 0 terminated list. */
|
|
|
+};
|
|
|
+
|
|
|
+MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
|
|
|
+
|
|
|
+static struct pci_driver i3000_driver = {
|
|
|
+ .name = EDAC_MOD_STR,
|
|
|
+ .probe = i3000_init_one,
|
|
|
+ .remove = __devexit_p(i3000_remove_one),
|
|
|
+ .id_table = i3000_pci_tbl,
|
|
|
+};
|
|
|
+
|
|
|
+static int __init i3000_init(void)
|
|
|
+{
|
|
|
+ int pci_rc;
|
|
|
+
|
|
|
+ debugf3("MC: %s()\n", __func__);
|
|
|
+ pci_rc = pci_register_driver(&i3000_driver);
|
|
|
+ if (pci_rc < 0)
|
|
|
+ goto fail0;
|
|
|
+
|
|
|
+ if (mci_pdev == NULL) {
|
|
|
+ i3000_registered = 0;
|
|
|
+ mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
|
|
|
+ PCI_DEVICE_ID_INTEL_3000_HB, NULL);
|
|
|
+ if (!mci_pdev) {
|
|
|
+ debugf0("i3000 pci_get_device fail\n");
|
|
|
+ pci_rc = -ENODEV;
|
|
|
+ goto fail1;
|
|
|
+ }
|
|
|
+
|
|
|
+ pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
|
|
|
+ if (pci_rc < 0) {
|
|
|
+ debugf0("i3000 init fail\n");
|
|
|
+ pci_rc = -ENODEV;
|
|
|
+ goto fail1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+fail1:
|
|
|
+ pci_unregister_driver(&i3000_driver);
|
|
|
+
|
|
|
+fail0:
|
|
|
+ if (mci_pdev)
|
|
|
+ pci_dev_put(mci_pdev);
|
|
|
+
|
|
|
+ return pci_rc;
|
|
|
+}
|
|
|
+
|
|
|
+static void __exit i3000_exit(void)
|
|
|
+{
|
|
|
+ debugf3("MC: %s()\n", __func__);
|
|
|
+
|
|
|
+ pci_unregister_driver(&i3000_driver);
|
|
|
+ if (!i3000_registered) {
|
|
|
+ i3000_remove_one(mci_pdev);
|
|
|
+ pci_dev_put(mci_pdev);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+module_init(i3000_init);
|
|
|
+module_exit(i3000_exit);
|
|
|
+
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
|
|
|
+MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
|