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@@ -1,502 +0,0 @@
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-/*
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- * bonito board support
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- *
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- * Copyright (C) 2011 Renesas Solutions Corp.
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- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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- *
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- */
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-
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-#include <linux/kernel.h>
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-#include <linux/i2c.h>
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-#include <linux/init.h>
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-#include <linux/interrupt.h>
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-#include <linux/irq.h>
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-#include <linux/pinctrl/machine.h>
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-#include <linux/platform_device.h>
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-#include <linux/gpio.h>
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-#include <linux/regulator/fixed.h>
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-#include <linux/regulator/machine.h>
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-#include <linux/smsc911x.h>
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-#include <linux/videodev2.h>
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-#include <mach/common.h>
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-#include <asm/mach-types.h>
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-#include <asm/mach/arch.h>
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-#include <asm/mach/map.h>
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-#include <asm/mach/time.h>
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-#include <asm/hardware/cache-l2x0.h>
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-#include <mach/r8a7740.h>
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-#include <mach/irqs.h>
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-#include <video/sh_mobile_lcdc.h>
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-
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-/*
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- * CS Address device note
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- *----------------------------------------------------------------
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- * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
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- * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
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- * 4 -
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- * 5A -
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- * 5B 0x1600_0000 SRAM (8MB)
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- * 6 0x1800_0000 FPGA (64K)
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- * 0x1801_0000 Ether (4KB)
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- * 0x1801_1000 USB (4KB)
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- */
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-
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-/*
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- * SW12
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- *
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- * bit1 bit2 bit3
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- *----------------------------------------------------------------------------
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- * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
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- * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
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- */
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-
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-/*
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- * SCIFA5 (CN42)
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- *
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- * S38.3 = ON
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- * S39.6 = ON
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- * S43.1 = ON
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- */
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-
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-/*
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- * LCDC0 (CN3/CN4/CN7)
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- *
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- * S38.1 = OFF
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- * S38.2 = OFF
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- */
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-
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-/* Dummy supplies, where voltage doesn't matter */
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-static struct regulator_consumer_supply dummy_supplies[] = {
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- REGULATOR_SUPPLY("vddvario", "smsc911x"),
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- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
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-};
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-
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-/*
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- * FPGA
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- */
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-#define IRQSR0 0x0020
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-#define IRQSR1 0x0022
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-#define IRQMR0 0x0030
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-#define IRQMR1 0x0032
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-#define BUSSWMR1 0x0070
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-#define BUSSWMR2 0x0072
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-#define BUSSWMR3 0x0074
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-#define BUSSWMR4 0x0076
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-
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-#define LCDCR 0x10B4
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-#define DEVRSTCR1 0x10D0
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-#define DEVRSTCR2 0x10D2
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-#define A1MDSR 0x10E0
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-#define BVERR 0x1100
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-
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-/* FPGA IRQ */
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-#define FPGA_IRQ_BASE (512)
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-#define FPGA_IRQ0 (FPGA_IRQ_BASE)
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-#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
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-#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
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-static u16 bonito_fpga_read(u32 offset)
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-{
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- return __raw_readw(IOMEM(0xf0003000) + offset);
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-}
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-
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-static void bonito_fpga_write(u32 offset, u16 val)
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-{
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- __raw_writew(val, IOMEM(0xf0003000) + offset);
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-}
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-
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-static void bonito_fpga_irq_disable(struct irq_data *data)
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-{
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- unsigned int irq = data->irq;
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- u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
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- int shift = irq % 16;
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-
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- bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
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-}
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-
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-static void bonito_fpga_irq_enable(struct irq_data *data)
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-{
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- unsigned int irq = data->irq;
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- u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
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- int shift = irq % 16;
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-
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- bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
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-}
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-
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-static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
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- .name = "bonito FPGA",
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- .irq_mask = bonito_fpga_irq_disable,
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- .irq_unmask = bonito_fpga_irq_enable,
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-};
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-
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-static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
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-{
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- u32 val = bonito_fpga_read(IRQSR1) << 16 |
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- bonito_fpga_read(IRQSR0);
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- u32 mask = bonito_fpga_read(IRQMR1) << 16 |
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- bonito_fpga_read(IRQMR0);
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-
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- int i;
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-
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- val &= ~mask;
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-
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- for (i = 0; i < 32; i++) {
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- if (!(val & (1 << i)))
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- continue;
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-
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- generic_handle_irq(FPGA_IRQ_BASE + i);
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- }
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-}
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-
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-static void bonito_fpga_init(void)
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-{
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- int i;
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-
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- bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
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- bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
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-
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- /* Device reset */
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- bonito_fpga_write(DEVRSTCR1,
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- (1 << 2)); /* Eth */
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-
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- /* FPGA irq require special handling */
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- for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
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- irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
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- handle_level_irq, "level");
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- set_irq_flags(i, IRQF_VALID); /* yuck */
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- }
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-
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- irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
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- irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
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-}
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-
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-/*
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-* PMIC settings
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-*
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-* FIXME
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-*
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-* bonito board needs some settings by pmic which use i2c access.
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-* pmic settings use device_initcall() here for use it.
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-*/
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-static __u8 *pmic_settings = NULL;
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-static __u8 pmic_do_2A[] = {
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- 0x1C, 0x09,
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- 0x1A, 0x80,
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- 0xff, 0xff,
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-};
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-
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-static int __init pmic_init(void)
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-{
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- struct i2c_adapter *a = i2c_get_adapter(0);
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- struct i2c_msg msg;
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- __u8 buf[2];
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- int i, ret;
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-
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- if (!pmic_settings)
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- return 0;
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- if (!a)
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- return 0;
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-
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- msg.addr = 0x46;
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- msg.buf = buf;
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- msg.len = 2;
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- msg.flags = 0;
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-
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- for (i = 0; ; i += 2) {
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- buf[0] = pmic_settings[i + 0];
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- buf[1] = pmic_settings[i + 1];
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-
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- if ((0xff == buf[0]) && (0xff == buf[1]))
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- break;
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-
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- ret = i2c_transfer(a, &msg, 1);
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- if (ret < 0) {
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- pr_err("i2c transfer fail\n");
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- break;
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- }
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- }
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-
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- return 0;
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-}
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-device_initcall(pmic_init);
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-
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-/*
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- * LCDC0
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- */
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-static const struct fb_videomode lcdc0_mode = {
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- .name = "WVGA Panel",
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- .xres = 800,
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- .yres = 480,
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- .left_margin = 88,
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- .right_margin = 40,
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- .hsync_len = 128,
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- .upper_margin = 20,
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- .lower_margin = 5,
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- .vsync_len = 5,
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- .sync = 0,
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-};
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-
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-static struct sh_mobile_lcdc_info lcdc0_info = {
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- .clock_source = LCDC_CLK_BUS,
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- .ch[0] = {
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- .chan = LCDC_CHAN_MAINLCD,
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- .fourcc = V4L2_PIX_FMT_RGB565,
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- .interface_type = RGB24,
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- .clock_divider = 5,
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- .flags = 0,
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- .lcd_modes = &lcdc0_mode,
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- .num_modes = 1,
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- .panel_cfg = {
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- .width = 152,
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- .height = 91,
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- },
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- },
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-};
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-
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-static struct resource lcdc0_resources[] = {
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- [0] = {
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- .name = "LCDC0",
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- .start = 0xfe940000,
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- .end = 0xfe943fff,
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- .flags = IORESOURCE_MEM,
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- },
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- [1] = {
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- .start = intcs_evt2irq(0x0580),
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- .flags = IORESOURCE_IRQ,
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- },
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-};
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-
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-static struct platform_device lcdc0_device = {
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- .name = "sh_mobile_lcdc_fb",
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- .id = 0,
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- .resource = lcdc0_resources,
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- .num_resources = ARRAY_SIZE(lcdc0_resources),
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- .dev = {
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- .platform_data = &lcdc0_info,
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- .coherent_dma_mask = ~0,
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- },
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-};
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-
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-static const struct pinctrl_map lcdc0_pinctrl_map[] = {
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- /* LCD0 */
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- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
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- "lcd0_data24_1", "lcd0"),
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- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
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- "lcd0_lclk_1", "lcd0"),
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- PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
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- "lcd0_sync", "lcd0"),
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-};
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-
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-/*
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- * SMSC 9221
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- */
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-static struct resource smsc_resources[] = {
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- [0] = {
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- .start = 0x18010000,
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- .end = 0x18011000 - 1,
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- .flags = IORESOURCE_MEM,
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- },
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- [1] = {
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- .start = FPGA_ETH_IRQ,
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- .flags = IORESOURCE_IRQ,
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- },
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-};
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-
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-static struct smsc911x_platform_config smsc_platdata = {
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- .flags = SMSC911X_USE_16BIT,
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- .phy_interface = PHY_INTERFACE_MODE_MII,
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- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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-};
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-
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-static struct platform_device smsc_device = {
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- .name = "smsc911x",
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- .dev = {
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- .platform_data = &smsc_platdata,
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- },
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- .resource = smsc_resources,
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- .num_resources = ARRAY_SIZE(smsc_resources),
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-};
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-
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-/*
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- * base board devices
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- */
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-static struct platform_device *bonito_base_devices[] __initdata = {
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- &lcdc0_device,
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- &smsc_device,
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-};
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-
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-/*
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- * map I/O
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- */
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-static struct map_desc bonito_io_desc[] __initdata = {
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- /*
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- * for FPGA (0x1800000-0x19ffffff)
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- * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
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- */
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- {
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- .virtual = 0xf0003000,
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- .pfn = __phys_to_pfn(0x18000000),
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- .length = PAGE_SIZE * 2,
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- .type = MT_DEVICE_NONSHARED
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- }
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-};
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-
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-static void __init bonito_map_io(void)
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-{
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- r8a7740_map_io();
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- iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
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-}
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-
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-/*
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- * board init
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- */
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-#define BIT_ON(sw, bit) (sw & (1 << bit))
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-#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
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-
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-#define VCCQ1CR IOMEM(0xE6058140)
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-#define VCCQ1LCDCR IOMEM(0xE6058186)
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-
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-/*
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- * HACK: The FPGA mappings should be associated with the FPGA device, but we
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- * don't have one at the moment. Associate them with the PFC device to make
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- * sure they will be applied.
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- */
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-static const struct pinctrl_map fpga_pinctrl_map[] = {
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- /* FPGA */
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- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
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- "bsc_cs5a_0", "bsc"),
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- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
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- "bsc_cs5b", "bsc"),
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- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
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- "bsc_cs6a", "bsc"),
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- PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
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- "intc_irq10", "intc"),
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-};
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-
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-static const struct pinctrl_map scifa5_pinctrl_map[] = {
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- /* SCIFA5 */
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- PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
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- "scifa5_data_2", "scifa5"),
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-};
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-
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-static void __init bonito_init(void)
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-{
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- u16 val;
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-
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- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
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-
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- pinctrl_register_mappings(fpga_pinctrl_map,
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- ARRAY_SIZE(fpga_pinctrl_map));
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- r8a7740_pinmux_init();
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- bonito_fpga_init();
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-
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- pmic_settings = pmic_do_2A;
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-
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- /*
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- * core board settings
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- */
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-
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-#ifdef CONFIG_CACHE_L2X0
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- /* Early BRESP enable, Shared attribute override enable, 32K*8way */
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- l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
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-#endif
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-
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- r8a7740_add_standard_devices();
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-
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- /*
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- * base board settings
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- */
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- gpio_request_one(176, GPIOF_IN, NULL);
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- if (!gpio_get_value(176)) {
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- u16 bsw2;
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- u16 bsw3;
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- u16 bsw4;
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-
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- val = bonito_fpga_read(BVERR);
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- pr_info("bonito version: cpu %02x, base %02x\n",
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- ((val >> 8) & 0xFF),
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- ((val >> 0) & 0xFF));
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-
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- bsw2 = bonito_fpga_read(BUSSWMR2);
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- bsw3 = bonito_fpga_read(BUSSWMR3);
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- bsw4 = bonito_fpga_read(BUSSWMR4);
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-
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- /*
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- * SCIFA5 (CN42)
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- */
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- if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
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- BIT_OFF(bsw3, 9) && /* S39.6 = ON */
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- BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
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- pinctrl_register_mappings(scifa5_pinctrl_map,
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- ARRAY_SIZE(scifa5_pinctrl_map));
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- }
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-
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- /*
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- * LCDC0 (CN3)
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- */
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- if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
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- BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
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- pinctrl_register_mappings(lcdc0_pinctrl_map,
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- ARRAY_SIZE(lcdc0_pinctrl_map));
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-
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- gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
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- NULL); /* LCDDON */
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-
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- /* backlight on */
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- bonito_fpga_write(LCDCR, 1);
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-
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- /* drivability Max */
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- __raw_writew(0x00FF , VCCQ1LCDCR);
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- __raw_writew(0xFFFF , VCCQ1CR);
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- }
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-
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- platform_add_devices(bonito_base_devices,
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- ARRAY_SIZE(bonito_base_devices));
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- }
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-}
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-
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-static void __init bonito_earlytimer_init(void)
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-{
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- u16 val;
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- u8 md_ck = 0;
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-
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- /* read MD_CK value */
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- val = bonito_fpga_read(A1MDSR);
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- if (val & (1 << 10))
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- md_ck |= MD_CK2;
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- if (val & (1 << 9))
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- md_ck |= MD_CK1;
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- if (val & (1 << 8))
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- md_ck |= MD_CK0;
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-
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- r8a7740_clock_init(md_ck);
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- shmobile_earlytimer_init();
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-}
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-
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-static void __init bonito_add_early_devices(void)
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-{
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- r8a7740_add_early_devices();
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-}
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-
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-MACHINE_START(BONITO, "bonito")
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- .map_io = bonito_map_io,
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- .init_early = bonito_add_early_devices,
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- .init_irq = r8a7740_init_irq,
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- .handle_irq = shmobile_handle_irq_intc,
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- .init_machine = bonito_init,
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- .init_late = shmobile_init_late,
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- .init_time = bonito_earlytimer_init,
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-MACHINE_END
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Kuninori Morimoto