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@@ -253,32 +253,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
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BUG_ON(src % 4);
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BUG_ON(size % 4);
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- /* Force a sync in case a previous config reset on this channel
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- * occurred. This is needed so subsequent writes to DMA registers
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- * are not spuriously lost/corrupted.
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- */
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- __builtin_bfin_ssync();
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-
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src_ch = 0;
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/* Find an avalible memDMA channel */
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while (1) {
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- if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) {
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- dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
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- src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
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- } else {
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+ if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
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dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
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src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
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+ } else {
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+ dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
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+ src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
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}
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- if (!bfin_read16(&src_ch->cfg)) {
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+ if (!bfin_read16(&src_ch->cfg))
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+ break;
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+ else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
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+ bfin_write16(&src_ch->cfg, 0);
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break;
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- } else {
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- if (bfin_read16(&src_ch->irq_status) & DMA_DONE)
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- bfin_write16(&src_ch->cfg, 0);
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}
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-
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}
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+ /* Force a sync in case a previous config reset on this channel
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+ * occurred. This is needed so subsequent writes to DMA registers
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+ * are not spuriously lost/corrupted.
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+ */
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+ __builtin_bfin_ssync();
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+
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/* Destination */
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bfin_write32(&dst_ch->start_addr, dst);
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bfin_write16(&dst_ch->x_count, size >> 2);
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