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@@ -3565,3 +3565,46 @@ void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
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dev_data->errata |= (1 << erratum);
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dev_data->errata |= (1 << erratum);
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}
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}
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EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
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EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
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+
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+int amd_iommu_device_info(struct pci_dev *pdev,
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+ struct amd_iommu_device_info *info)
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+{
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+ int max_pasids;
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+ int pos;
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+
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+ if (pdev == NULL || info == NULL)
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+ return -EINVAL;
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+
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+ if (!amd_iommu_v2_supported())
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+ return -EINVAL;
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+
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+ memset(info, 0, sizeof(*info));
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+
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+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
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+ if (pos)
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+ info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
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+
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+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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+ if (pos)
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+ info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
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+
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+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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+ if (pos) {
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+ int features;
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+
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+ max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
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+ max_pasids = min(max_pasids, (1 << 20));
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+
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+ info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
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+ info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
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+
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+ features = pci_pasid_features(pdev);
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+ if (features & PCI_PASID_CAP_EXEC)
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+ info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
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+ if (features & PCI_PASID_CAP_PRIV)
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+ info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
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+ }
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL(amd_iommu_device_info);
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