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@@ -1803,9 +1803,60 @@ static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
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{
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struct b43_phy_n *nphy = dev->phy.n;
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u16 *save = nphy->tx_rx_cal_radio_saveregs;
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+ u16 tmp;
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+ u8 offset, i;
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if (dev->phy.rev >= 3) {
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- /* TODO */
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+ for (i = 0; i < 2; i++) {
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+ tmp = (i == 0) ? 0x2000 : 0x3000;
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+ offset = i * 11;
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+
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+ save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
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+ save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
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+ save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
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+ save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
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+ save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
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+ save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
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+ save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
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+ save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
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+ save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
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+ save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
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+ save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
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+
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+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
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+ b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
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+ b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
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+ b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
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+ b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
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+ b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
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+ if (nphy->ipa5g_on) {
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+ b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
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+ b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
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+ } else {
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+ b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
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+ b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
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+ }
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+ b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
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+ } else {
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+ b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
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+ b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
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+ b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
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+ b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
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+ b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
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+ b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
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+ if (nphy->ipa2g_on) {
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+ b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
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+ b43_radio_write16(dev, tmp | B2055_XOCTL2,
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+ (dev->phy.rev < 5) ? 0x11 : 0x01);
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+ } else {
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+ b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
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+ b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
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+ }
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+ }
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+ b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
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+ b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
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+ b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
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+ }
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} else {
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save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
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b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
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