|
@@ -139,13 +139,12 @@ static void asic3_irq_flip_edge(struct asic3 *asic,
|
|
|
|
|
|
static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
|
|
|
{
|
|
|
+ struct asic3 *asic = irq_desc_get_handler_data(desc);
|
|
|
+ struct irq_data *data = irq_desc_get_irq_data(desc);
|
|
|
int iter, i;
|
|
|
unsigned long flags;
|
|
|
- struct asic3 *asic;
|
|
|
-
|
|
|
- desc->irq_data.chip->irq_ack(&desc->irq_data);
|
|
|
|
|
|
- asic = get_irq_data(irq);
|
|
|
+ data->chip->irq_ack(irq_data);
|
|
|
|
|
|
for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
|
|
|
u32 status;
|
|
@@ -188,8 +187,7 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
|
|
|
irqnr = asic->irq_base +
|
|
|
(ASIC3_GPIOS_PER_BANK * bank)
|
|
|
+ i;
|
|
|
- desc = irq_to_desc(irqnr);
|
|
|
- desc->handle_irq(irqnr, desc);
|
|
|
+ generic_handle_irq(irqnr);
|
|
|
if (asic->irq_bothedge[bank] & bit)
|
|
|
asic3_irq_flip_edge(asic, base,
|
|
|
bit);
|
|
@@ -200,11 +198,8 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
|
|
|
/* Handle remaining IRQs in the status register */
|
|
|
for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
|
|
|
/* They start at bit 4 and go up */
|
|
|
- if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
|
|
|
- desc = irq_to_desc(asic->irq_base + i);
|
|
|
- desc->handle_irq(asic->irq_base + i,
|
|
|
- desc);
|
|
|
- }
|
|
|
+ if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
|
|
|
+ generic_handle_irq(asic->irq_base + i);
|
|
|
}
|
|
|
}
|
|
|
|