Setting GPIO_0 pad as clko1 clock output to provide MCLK for WM8962. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
@@ -29,6 +29,7 @@
MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+ MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
@@ -33,6 +33,7 @@
MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+ MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0