|
@@ -101,16 +101,13 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
|
|
|
*/
|
|
|
static int iommu_completion_wait(struct amd_iommu *iommu)
|
|
|
{
|
|
|
- int ret;
|
|
|
+ int ret, ready = 0;
|
|
|
+ unsigned status = 0;
|
|
|
struct iommu_cmd cmd;
|
|
|
- volatile u64 ready = 0;
|
|
|
- unsigned long ready_phys = virt_to_phys(&ready);
|
|
|
unsigned long i = 0;
|
|
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
|
- cmd.data[0] = LOW_U32(ready_phys) | CMD_COMPL_WAIT_STORE_MASK;
|
|
|
- cmd.data[1] = upper_32_bits(ready_phys);
|
|
|
- cmd.data[2] = 1; /* value written to 'ready' */
|
|
|
+ cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
|
|
|
CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
|
|
|
|
|
|
iommu->need_sync = 0;
|
|
@@ -122,9 +119,15 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
|
|
|
|
|
|
while (!ready && (i < EXIT_LOOP_COUNT)) {
|
|
|
++i;
|
|
|
- cpu_relax();
|
|
|
+ /* wait for the bit to become one */
|
|
|
+ status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
|
|
|
+ ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
|
|
|
}
|
|
|
|
|
|
+ /* set bit back to zero */
|
|
|
+ status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
|
|
|
+ writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
|
|
|
+
|
|
|
if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
|
|
|
printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
|
|
|
|