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@@ -55,7 +55,7 @@ static int debug;
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static struct {u8 reg; u8 data;} cx24110_regdata[]=
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static struct {u8 reg; u8 data;} cx24110_regdata[]=
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/* Comments beginning with @ denote this value should
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/* Comments beginning with @ denote this value should
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- be the default */
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+ be the default */
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{{0x09,0x01}, /* SoftResetAll */
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{{0x09,0x01}, /* SoftResetAll */
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{0x09,0x00}, /* release reset */
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{0x09,0x00}, /* release reset */
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{0x01,0xe8}, /* MSB of code rate 27.5MS/s */
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{0x01,0xe8}, /* MSB of code rate 27.5MS/s */
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@@ -66,26 +66,26 @@ static struct {u8 reg; u8 data;} cx24110_regdata[]=
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{0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
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{0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
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{0x0a,0x00}, /* @ partial chip disables, do not set */
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{0x0a,0x00}, /* @ partial chip disables, do not set */
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{0x0b,0x01}, /* set output clock in gapped mode, start signal low
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{0x0b,0x01}, /* set output clock in gapped mode, start signal low
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- active for first byte */
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+ active for first byte */
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{0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
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{0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
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{0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
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{0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
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{0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
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{0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
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- to avoid starting the BER counter. Reset the
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- CRC test bit. Finite counting selected */
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+ to avoid starting the BER counter. Reset the
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+ CRC test bit. Finite counting selected */
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{0x15,0xff}, /* @ size of the limited time window for RS BER
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{0x15,0xff}, /* @ size of the limited time window for RS BER
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- estimation. It is <value>*256 RS blocks, this
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- gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
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+ estimation. It is <value>*256 RS blocks, this
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+ gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
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{0x16,0x00}, /* @ enable all RS output ports */
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{0x16,0x00}, /* @ enable all RS output ports */
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{0x17,0x04}, /* @ time window allowed for the RS to sync */
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{0x17,0x04}, /* @ time window allowed for the RS to sync */
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{0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
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{0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
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- for automatically */
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+ for automatically */
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/* leave the current code rate and normalization
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/* leave the current code rate and normalization
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- registers as they are after reset... */
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+ registers as they are after reset... */
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{0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
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{0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
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- only once */
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+ only once */
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{0x23,0x18}, /* @ size of the limited time window for Viterbi BER
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{0x23,0x18}, /* @ size of the limited time window for Viterbi BER
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- estimation. It is <value>*65536 channel bits, i.e.
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- approx. 38ms at 27.5MS/s, rate 3/4 */
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+ estimation. It is <value>*65536 channel bits, i.e.
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+ approx. 38ms at 27.5MS/s, rate 3/4 */
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{0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
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{0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
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/* leave front-end AGC parameters at default values */
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/* leave front-end AGC parameters at default values */
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/* leave decimation AGC parameters at default values */
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/* leave decimation AGC parameters at default values */
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