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@@ -292,7 +292,7 @@ unknown:
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*/
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*/
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static int ael2005_setup_sr_edc(struct cphy *phy)
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static int ael2005_setup_sr_edc(struct cphy *phy)
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{
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{
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- static struct reg_val regs[] = {
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+ static const struct reg_val regs[] = {
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{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
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{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
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{ MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
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{ MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
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{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
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{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
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@@ -324,11 +324,11 @@ static int ael2005_setup_sr_edc(struct cphy *phy)
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static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
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static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
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{
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{
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- static struct reg_val regs[] = {
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+ static const struct reg_val regs[] = {
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{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
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{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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};
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};
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- static struct reg_val preemphasis[] = {
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+ static const struct reg_val preemphasis[] = {
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{ MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
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{ MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
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{ MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
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{ MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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@@ -393,7 +393,7 @@ static int ael2005_intr_clear(struct cphy *phy)
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static int ael2005_reset(struct cphy *phy, int wait)
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static int ael2005_reset(struct cphy *phy, int wait)
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{
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{
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- static struct reg_val regs0[] = {
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+ static const struct reg_val regs0[] = {
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{ MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
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{ MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
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{ MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
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{ MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
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{ MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
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{ MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
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@@ -403,7 +403,7 @@ static int ael2005_reset(struct cphy *phy, int wait)
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{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
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{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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};
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};
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- static struct reg_val regs1[] = {
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+ static const struct reg_val regs1[] = {
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{ MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
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{ MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
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{ MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
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{ MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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@@ -522,7 +522,7 @@ int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
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*/
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*/
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static int ael2020_setup_sr_edc(struct cphy *phy)
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static int ael2020_setup_sr_edc(struct cphy *phy)
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{
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{
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- static struct reg_val regs[] = {
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+ static const struct reg_val regs[] = {
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/* set CDR offset to 10 */
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/* set CDR offset to 10 */
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{ MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
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{ MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
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@@ -551,20 +551,20 @@ static int ael2020_setup_sr_edc(struct cphy *phy)
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static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
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static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
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{
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{
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/* set uC to 40MHz */
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/* set uC to 40MHz */
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- static struct reg_val uCclock40MHz[] = {
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+ static const struct reg_val uCclock40MHz[] = {
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{ MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
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{ MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
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{ MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
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{ MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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};
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};
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/* activate uC clock */
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/* activate uC clock */
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- static struct reg_val uCclockActivate[] = {
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+ static const struct reg_val uCclockActivate[] = {
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{ MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
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{ MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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};
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};
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/* set PC to start of SRAM and activate uC */
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/* set PC to start of SRAM and activate uC */
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- static struct reg_val uCactivate[] = {
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+ static const struct reg_val uCactivate[] = {
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{ MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
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{ MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
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{ MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
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{ MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
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{ 0, 0, 0, 0 }
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{ 0, 0, 0, 0 }
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@@ -624,7 +624,7 @@ static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
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*/
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*/
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static int ael2020_intr_enable(struct cphy *phy)
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static int ael2020_intr_enable(struct cphy *phy)
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{
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{
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- struct reg_val regs[] = {
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+ static const struct reg_val regs[] = {
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/* output Module's Loss Of Signal (LOS) to LED */
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/* output Module's Loss Of Signal (LOS) to LED */
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{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
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{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
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0xffff, 0x4 },
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0xffff, 0x4 },
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@@ -664,7 +664,7 @@ static int ael2020_intr_enable(struct cphy *phy)
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*/
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*/
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static int ael2020_intr_disable(struct cphy *phy)
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static int ael2020_intr_disable(struct cphy *phy)
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{
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{
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- struct reg_val regs[] = {
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+ static const struct reg_val regs[] = {
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/* reset "link status" LED to "off" */
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/* reset "link status" LED to "off" */
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{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
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{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
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0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },
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0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },
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@@ -701,7 +701,7 @@ static int ael2020_intr_clear(struct cphy *phy)
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return err ? err : t3_phy_lasi_intr_clear(phy);
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return err ? err : t3_phy_lasi_intr_clear(phy);
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}
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}
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-static struct reg_val ael2020_reset_regs[] = {
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+static const struct reg_val ael2020_reset_regs[] = {
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/* Erratum #2: CDRLOL asserted, causing PMA link down status */
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/* Erratum #2: CDRLOL asserted, causing PMA link down status */
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{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
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{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
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