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+/*
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+ * machine_kexec.c - handle transition of Linux booting another kernel
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+ * Copyright (C) 2002-2005 Eric Biederman <ebiederm@xmission.com>
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+ *
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+ * This source code is licensed under the GNU General Public License,
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+ * Version 2. See the file COPYING for more details.
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+ */
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+
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+#include <linux/mm.h>
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+#include <linux/kexec.h>
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+#include <linux/delay.h>
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+#include <asm/pgtable.h>
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+#include <asm/pgalloc.h>
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+#include <asm/tlbflush.h>
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+#include <asm/mmu_context.h>
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+#include <asm/io.h>
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+#include <asm/apic.h>
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+#include <asm/cpufeature.h>
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+
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+static inline unsigned long read_cr3(void)
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+{
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+ unsigned long cr3;
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+ asm volatile("movl %%cr3,%0": "=r"(cr3));
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+ return cr3;
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+}
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+
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+#define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
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+
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+#define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
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+#define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
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+#define L2_ATTR (_PAGE_PRESENT)
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+
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+#define LEVEL0_SIZE (1UL << 12UL)
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+
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+#ifndef CONFIG_X86_PAE
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+#define LEVEL1_SIZE (1UL << 22UL)
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+static u32 pgtable_level1[1024] PAGE_ALIGNED;
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+
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+static void identity_map_page(unsigned long address)
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+{
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+ unsigned long level1_index, level2_index;
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+ u32 *pgtable_level2;
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+
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+ /* Find the current page table */
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+ pgtable_level2 = __va(read_cr3());
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+
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+ /* Find the indexes of the physical address to identity map */
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+ level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
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+ level2_index = address / LEVEL1_SIZE;
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+
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+ /* Identity map the page table entry */
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+ pgtable_level1[level1_index] = address | L0_ATTR;
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+ pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
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+
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+ /* Flush the tlb so the new mapping takes effect.
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+ * Global tlb entries are not flushed but that is not an issue.
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+ */
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+ load_cr3(pgtable_level2);
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+}
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+
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+#else
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+#define LEVEL1_SIZE (1UL << 21UL)
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+#define LEVEL2_SIZE (1UL << 30UL)
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+static u64 pgtable_level1[512] PAGE_ALIGNED;
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+static u64 pgtable_level2[512] PAGE_ALIGNED;
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+
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+static void identity_map_page(unsigned long address)
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+{
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+ unsigned long level1_index, level2_index, level3_index;
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+ u64 *pgtable_level3;
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+
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+ /* Find the current page table */
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+ pgtable_level3 = __va(read_cr3());
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+
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+ /* Find the indexes of the physical address to identity map */
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+ level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
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+ level2_index = (address % LEVEL2_SIZE)/LEVEL1_SIZE;
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+ level3_index = address / LEVEL2_SIZE;
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+
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+ /* Identity map the page table entry */
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+ pgtable_level1[level1_index] = address | L0_ATTR;
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+ pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
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+ set_64bit(&pgtable_level3[level3_index], __pa(pgtable_level2) | L2_ATTR);
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+
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+ /* Flush the tlb so the new mapping takes effect.
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+ * Global tlb entries are not flushed but that is not an issue.
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+ */
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+ load_cr3(pgtable_level3);
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+}
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+#endif
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+
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+
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+static void set_idt(void *newidt, __u16 limit)
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+{
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+ unsigned char curidt[6];
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+
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+ /* ia32 supports unaliged loads & stores */
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+ (*(__u16 *)(curidt)) = limit;
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+ (*(__u32 *)(curidt +2)) = (unsigned long)(newidt);
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+
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+ __asm__ __volatile__ (
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+ "lidt %0\n"
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+ : "=m" (curidt)
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+ );
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+};
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+
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+
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+static void set_gdt(void *newgdt, __u16 limit)
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+{
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+ unsigned char curgdt[6];
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+
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+ /* ia32 supports unaligned loads & stores */
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+ (*(__u16 *)(curgdt)) = limit;
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+ (*(__u32 *)(curgdt +2)) = (unsigned long)(newgdt);
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+
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+ __asm__ __volatile__ (
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+ "lgdt %0\n"
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+ : "=m" (curgdt)
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+ );
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+};
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+
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+static void load_segments(void)
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+{
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+#define __STR(X) #X
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+#define STR(X) __STR(X)
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+
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+ __asm__ __volatile__ (
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+ "\tljmp $"STR(__KERNEL_CS)",$1f\n"
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+ "\t1:\n"
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+ "\tmovl $"STR(__KERNEL_DS)",%eax\n"
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+ "\tmovl %eax,%ds\n"
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+ "\tmovl %eax,%es\n"
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+ "\tmovl %eax,%fs\n"
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+ "\tmovl %eax,%gs\n"
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+ "\tmovl %eax,%ss\n"
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+ );
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+#undef STR
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+#undef __STR
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+}
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+
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+typedef asmlinkage NORET_TYPE void (*relocate_new_kernel_t)(
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+ unsigned long indirection_page, unsigned long reboot_code_buffer,
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+ unsigned long start_address, unsigned int has_pae) ATTRIB_NORET;
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+
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+const extern unsigned char relocate_new_kernel[];
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+extern void relocate_new_kernel_end(void);
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+const extern unsigned int relocate_new_kernel_size;
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+
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+/*
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+ * A architecture hook called to validate the
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+ * proposed image and prepare the control pages
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+ * as needed. The pages for KEXEC_CONTROL_CODE_SIZE
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+ * have been allocated, but the segments have yet
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+ * been copied into the kernel.
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+ *
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+ * Do what every setup is needed on image and the
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+ * reboot code buffer to allow us to avoid allocations
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+ * later.
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+ *
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+ * Currently nothing.
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+ */
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+int machine_kexec_prepare(struct kimage *image)
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+{
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+ return 0;
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+}
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+
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+/*
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+ * Undo anything leftover by machine_kexec_prepare
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+ * when an image is freed.
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+ */
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+void machine_kexec_cleanup(struct kimage *image)
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+{
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+}
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+
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+/*
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+ * Do not allocate memory (or fail in any way) in machine_kexec().
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+ * We are past the point of no return, committed to rebooting now.
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+ */
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+NORET_TYPE void machine_kexec(struct kimage *image)
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+{
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+ unsigned long page_list;
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+ unsigned long reboot_code_buffer;
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+ relocate_new_kernel_t rnk;
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+
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+ /* Interrupts aren't acceptable while we reboot */
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+ local_irq_disable();
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+
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+ /* Compute some offsets */
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+ reboot_code_buffer = page_to_pfn(image->control_code_page) << PAGE_SHIFT;
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+ page_list = image->head;
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+
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+ /* Set up an identity mapping for the reboot_code_buffer */
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+ identity_map_page(reboot_code_buffer);
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+
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+ /* copy it out */
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+ memcpy((void *)reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size);
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+
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+ /* The segment registers are funny things, they are
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+ * automatically loaded from a table, in memory wherever you
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+ * set them to a specific selector, but this table is never
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+ * accessed again you set the segment to a different selector.
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+ *
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+ * The more common model is are caches where the behide
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+ * the scenes work is done, but is also dropped at arbitrary
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+ * times.
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+ *
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+ * I take advantage of this here by force loading the
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+ * segments, before I zap the gdt with an invalid value.
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+ */
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+ load_segments();
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+ /* The gdt & idt are now invalid.
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+ * If you want to load them you must set up your own idt & gdt.
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+ */
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+ set_gdt(phys_to_virt(0),0);
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+ set_idt(phys_to_virt(0),0);
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+
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+ /* now call it */
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+ rnk = (relocate_new_kernel_t) reboot_code_buffer;
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+ (*rnk)(page_list, reboot_code_buffer, image->start, cpu_has_pae);
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+}
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