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@@ -351,7 +351,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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*/
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ret_val = e1000e_phy_hw_reset_generic(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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/* Ungate automatic PHY configuration on non-managed 82579 */
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if ((hw->mac.type == e1000_pch2lan) &&
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@@ -366,7 +366,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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default:
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ret_val = e1000e_get_phy_id(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
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break;
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/* fall-through */
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@@ -377,10 +377,10 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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*/
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ret_val = e1000_set_mdio_slow_mode_hv(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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ret_val = e1000e_get_phy_id(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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break;
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}
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phy->type = e1000e_get_phy_type_from_id(phy->id);
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@@ -406,7 +406,6 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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break;
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}
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-out:
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return ret_val;
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}
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@@ -635,20 +634,18 @@ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
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u16 phy_reg;
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if (hw->phy.type != e1000_phy_82579)
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- goto out;
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+ return 0;
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ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if (hw->dev_spec.ich8lan.eee_disable)
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phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
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else
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phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
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- ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
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-out:
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- return ret_val;
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+ return e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
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}
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/**
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@@ -672,10 +669,8 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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* get_link_status flag is set upon receiving a Link Status
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* Change or Rx Sequence Error interrupt.
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*/
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- if (!mac->get_link_status) {
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- ret_val = 0;
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- goto out;
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- }
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+ if (!mac->get_link_status)
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+ return 0;
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/*
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* First we want to see if the MII Status Register reports
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@@ -684,16 +679,16 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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*/
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ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if (hw->mac.type == e1000_pchlan) {
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ret_val = e1000_k1_gig_workaround_hv(hw, link);
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if (ret_val)
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- goto out;
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+ return ret_val;
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}
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if (!link)
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- goto out; /* No link detected */
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+ return 0; /* No link detected */
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mac->get_link_status = false;
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@@ -701,13 +696,13 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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case e1000_pch2lan:
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ret_val = e1000_k1_workaround_lv(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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/* fall-thru */
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case e1000_pchlan:
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if (hw->phy.type == e1000_phy_82578) {
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ret_val = e1000_link_stall_workaround_hv(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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}
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/*
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@@ -737,16 +732,14 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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/* Enable/Disable EEE after link up */
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ret_val = e1000_set_eee_pchlan(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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/*
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* If we are forcing speed/duplex, then we simply return since
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* we have already determined whether we have link or not.
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*/
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- if (!mac->autoneg) {
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- ret_val = -E1000_ERR_CONFIG;
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- goto out;
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- }
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+ if (!mac->autoneg)
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+ return -E1000_ERR_CONFIG;
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/*
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* Auto-Neg is enabled. Auto Speed Detection takes care
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@@ -765,7 +758,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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if (ret_val)
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e_dbg("Error configuring flow control\n");
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-out:
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return ret_val;
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}
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@@ -1008,15 +1000,13 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
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ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
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if (ret_val)
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- goto out;
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+ return ret_val;
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phy_data &= ~HV_SMB_ADDR_MASK;
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phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
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phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
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- ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
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-out:
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- return ret_val;
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+ return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
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}
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/**
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@@ -1159,12 +1149,12 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
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if (hw->mac.type != e1000_pchlan)
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- goto out;
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+ return 0;
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/* Wrap the whole flow with the sw flag */
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
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if (link) {
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@@ -1218,7 +1208,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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release:
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hw->phy.ops.release(hw);
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-out:
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+
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return ret_val;
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}
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@@ -1244,7 +1234,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
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E1000_KMRNCTRLSTA_K1_CONFIG,
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&kmrn_reg);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if (k1_enable)
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kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
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@@ -1255,7 +1245,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
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E1000_KMRNCTRLSTA_K1_CONFIG,
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kmrn_reg);
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if (ret_val)
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- goto out;
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+ return ret_val;
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udelay(20);
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ctrl_ext = er32(CTRL_EXT);
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@@ -1273,8 +1263,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
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e1e_flush();
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udelay(20);
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-out:
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- return ret_val;
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+ return 0;
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}
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/**
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@@ -1376,13 +1365,13 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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u16 phy_data;
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if (hw->mac.type != e1000_pchlan)
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- return ret_val;
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+ return 0;
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|
|
/* Set MDIO slow mode before any other MDIO access */
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if (hw->phy.type == e1000_phy_82577) {
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ret_val = e1000_set_mdio_slow_mode_hv(hw);
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|
if (ret_val)
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|
- goto out;
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|
+ return ret_val;
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}
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|
|
|
if (((hw->phy.type == e1000_phy_82577) &&
|
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@@ -1419,7 +1408,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
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hw->phy.ops.release(hw);
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|
if (ret_val)
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|
- goto out;
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|
+ return ret_val;
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|
|
|
/*
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* Configure the K1 Si workaround during phy reset assuming there is
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@@ -1427,12 +1416,12 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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*/
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|
ret_val = e1000_k1_gig_workaround_hv(hw, true);
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|
if (ret_val)
|
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|
- goto out;
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|
+ return ret_val;
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|
|
|
|
|
/* Workaround for link disconnects on a busy hub in half duplex */
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|
|
ret_val = hw->phy.ops.acquire(hw);
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|
|
if (ret_val)
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|
|
- goto out;
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|
|
+ return ret_val;
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|
|
ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
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|
|
if (ret_val)
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|
|
goto release;
|
|
@@ -1440,7 +1429,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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|
phy_data & 0x00FF);
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|
release:
|
|
|
hw->phy.ops.release(hw);
|
|
|
-out:
|
|
|
+
|
|
|
return ret_val;
|
|
|
}
|
|
|
|
|
@@ -1497,13 +1486,13 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
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|
u16 i;
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|
|
|
|
if (hw->mac.type != e1000_pch2lan)
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|
- goto out;
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|
+ return 0;
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|
|
|
|
/* disable Rx path while enabling/disabling workaround */
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|
|
e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
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|
|
ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
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|
|
if (ret_val)
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|
|
- goto out;
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|
|
+ return ret_val;
|
|
|
|
|
|
if (enable) {
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|
|
/*
|
|
@@ -1545,24 +1534,24 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
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|
|
E1000_KMRNCTRLSTA_CTRL_OFFSET,
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|
|
&data);
|
|
|
if (ret_val)
|
|
|
- goto out;
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|
|
+ return ret_val;
|
|
|
ret_val = e1000e_write_kmrn_reg(hw,
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|
|
E1000_KMRNCTRLSTA_CTRL_OFFSET,
|
|
|
data | (1 << 0));
|
|
|
if (ret_val)
|
|
|
- goto out;
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|
|
+ return ret_val;
|
|
|
ret_val = e1000e_read_kmrn_reg(hw,
|
|
|
E1000_KMRNCTRLSTA_HD_CTRL,
|
|
|
&data);
|
|
|
if (ret_val)
|
|
|
- goto out;
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|
|
+ return ret_val;
|
|
|
data &= ~(0xF << 8);
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|
|
data |= (0xB << 8);
|
|
|
ret_val = e1000e_write_kmrn_reg(hw,
|
|
|
E1000_KMRNCTRLSTA_HD_CTRL,
|
|
|
data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
|
|
|
/* Enable jumbo frame workaround in the PHY */
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|
|
e1e_rphy(hw, PHY_REG(769, 23), &data);
|
|
@@ -1570,25 +1559,25 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
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|
|
data |= (0x37 << 5);
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|
|
ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
|
|
data &= ~(1 << 13);
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
e1e_rphy(hw, PHY_REG(776, 20), &data);
|
|
|
data &= ~(0x3FF << 2);
|
|
|
data |= (0x1A << 2);
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
e1e_rphy(hw, HV_PM_CTRL, &data);
|
|
|
ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
} else {
|
|
|
/* Write MAC register values back to h/w defaults */
|
|
|
mac_reg = er32(FFLT_DBG);
|
|
@@ -1603,56 +1592,53 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
|
|
|
E1000_KMRNCTRLSTA_CTRL_OFFSET,
|
|
|
&data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
ret_val = e1000e_write_kmrn_reg(hw,
|
|
|
E1000_KMRNCTRLSTA_CTRL_OFFSET,
|
|
|
data & ~(1 << 0));
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
ret_val = e1000e_read_kmrn_reg(hw,
|
|
|
E1000_KMRNCTRLSTA_HD_CTRL,
|
|
|
&data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
data &= ~(0xF << 8);
|
|
|
data |= (0xB << 8);
|
|
|
ret_val = e1000e_write_kmrn_reg(hw,
|
|
|
E1000_KMRNCTRLSTA_HD_CTRL,
|
|
|
data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
|
|
|
/* Write PHY register values back to h/w defaults */
|
|
|
e1e_rphy(hw, PHY_REG(769, 23), &data);
|
|
|
data &= ~(0x7F << 5);
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
|
|
data |= (1 << 13);
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
e1e_rphy(hw, PHY_REG(776, 20), &data);
|
|
|
data &= ~(0x3FF << 2);
|
|
|
data |= (0x8 << 2);
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
e1e_rphy(hw, HV_PM_CTRL, &data);
|
|
|
ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
|
|
|
if (ret_val)
|
|
|
- goto out;
|
|
|
+ return ret_val;
|
|
|
}
|
|
|
|
|
|
/* re-enable Rx path after enabling/disabling workaround */
|
|
|
- ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
|
|
|
-
|
|
|
-out:
|
|
|
- return ret_val;
|
|
|
+ return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
|
|
|
}
|
|
|
|
|
|
/**
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@@ -1664,14 +1650,14 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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s32 ret_val = 0;
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if (hw->mac.type != e1000_pch2lan)
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- goto out;
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+ return 0;
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/* Set MDIO slow mode before any other MDIO access */
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ret_val = e1000_set_mdio_slow_mode_hv(hw);
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
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I82579_MSE_THRESHOLD);
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if (ret_val)
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@@ -1689,7 +1675,6 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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release:
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hw->phy.ops.release(hw);
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-out:
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return ret_val;
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}
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@@ -1707,12 +1692,12 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
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u16 phy_reg;
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if (hw->mac.type != e1000_pch2lan)
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- goto out;
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+ return 0;
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/* Set K1 beacon duration based on 1Gbps speed or otherwise */
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ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
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== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
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@@ -1721,7 +1706,7 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
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ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if (status_reg & HV_M_STATUS_SPEED_1000) {
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mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
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@@ -1734,7 +1719,6 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
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ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
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}
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-out:
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return ret_val;
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}
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@@ -1805,7 +1789,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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u16 reg;
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if (e1000_check_reset_block(hw))
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- goto out;
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+ return 0;
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/* Allow time for h/w to get to quiescent state after reset */
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usleep_range(10000, 20000);
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@@ -1815,12 +1799,12 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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case e1000_pchlan:
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ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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break;
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case e1000_pch2lan:
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ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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break;
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default:
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break;
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@@ -1836,7 +1820,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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/* Configure the LCD with the extended configuration region in NVM */
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ret_val = e1000_sw_lcd_config_ich8lan(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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/* Configure the LCD with the OEM bits in NVM */
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ret_val = e1000_oem_bits_config_ich8lan(hw, true);
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@@ -1851,18 +1835,16 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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/* Set EEE LPI Update Timer to 200usec */
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
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I82579_LPI_UPDATE_TIMER);
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- if (ret_val)
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- goto release;
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- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
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- 0x1387);
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-release:
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+ if (!ret_val)
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+ ret_val = hw->phy.ops.write_reg_locked(hw,
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+ I82579_EMI_DATA,
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+ 0x1387);
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hw->phy.ops.release(hw);
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}
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-out:
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return ret_val;
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}
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@@ -1885,12 +1867,9 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
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ret_val = e1000e_phy_hw_reset_generic(hw);
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if (ret_val)
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- goto out;
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-
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- ret_val = e1000_post_phy_reset_ich8lan(hw);
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+ return ret_val;
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-out:
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- return ret_val;
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+ return e1000_post_phy_reset_ich8lan(hw);
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}
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/**
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@@ -1911,7 +1890,7 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
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ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
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if (ret_val)
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- goto out;
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+ return ret_val;
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if (active)
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oem_reg |= HV_OEM_BITS_LPLU;
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@@ -1921,10 +1900,7 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
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if (!e1000_check_reset_block(hw))
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oem_reg |= HV_OEM_BITS_RESTART_AN;
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- ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
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-
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-out:
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- return ret_val;
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+ return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
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}
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/**
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@@ -3001,7 +2977,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
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/* Get default ID LED modes */
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ret_val = hw->nvm.ops.valid_led_default(hw, &data);
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if (ret_val)
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- goto out;
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+ return ret_val;
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mac->ledctl_default = er32(LEDCTL);
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mac->ledctl_mode1 = mac->ledctl_default;
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@@ -3046,8 +3022,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
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}
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}
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-out:
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- return ret_val;
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+ return 0;
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}
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/**
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@@ -3162,11 +3137,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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if (ctrl & E1000_CTRL_PHY_RST) {
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ret_val = hw->phy.ops.get_cfg_done(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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ret_val = e1000_post_phy_reset_ich8lan(hw);
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if (ret_val)
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- goto out;
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+ return ret_val;
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}
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/*
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@@ -3184,8 +3159,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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kab |= E1000_KABGTXD_BGSQLBIAS;
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ew32(KABGTXD, kab);
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-out:
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- return ret_val;
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+ return 0;
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}
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/**
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