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@@ -160,7 +160,7 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
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IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
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txq->q.read_ptr, txq->q.write_ptr);
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- iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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+ iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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iwl_print_hex_error(trans, buf, sizeof(buf));
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@@ -173,9 +173,9 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
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u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
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bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
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u32 tbl_dw =
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- iwl_read_targ_mem(trans,
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- trans_pcie->scd_base_addr +
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- SCD_TRANS_TBL_OFFSET_QUEUE(i));
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+ iwl_trans_read_mem32(trans,
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+ trans_pcie->scd_base_addr +
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+ SCD_TRANS_TBL_OFFSET_QUEUE(i));
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if (i & 0x1)
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tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
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@@ -659,16 +659,16 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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/* reset conext data memory */
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for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
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a += 4)
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- iwl_write_targ_mem(trans, a, 0);
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+ iwl_trans_write_mem32(trans, a, 0);
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/* reset tx status memory */
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for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
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a += 4)
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- iwl_write_targ_mem(trans, a, 0);
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+ iwl_trans_write_mem32(trans, a, 0);
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for (; a < trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(
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trans->cfg->base_params->num_of_queues);
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a += 4)
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- iwl_write_targ_mem(trans, a, 0);
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+ iwl_trans_write_mem32(trans, a, 0);
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iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
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trans_pcie->scd_bc_tbls.dma >> 10);
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@@ -1005,14 +1005,14 @@ static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
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tbl_dw_addr = trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
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- tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
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+ tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
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if (txq_id & 0x1)
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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else
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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- iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
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+ iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
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return 0;
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}
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@@ -1071,9 +1071,9 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
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/* Set up Tx window size and frame limit for this queue */
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- iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
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+ iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
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- iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
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+ iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
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((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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@@ -1104,8 +1104,8 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
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iwl_pcie_txq_set_inactive(trans, txq_id);
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- _iwl_write_targ_mem_dwords(trans, stts_addr,
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- zero_val, ARRAY_SIZE(zero_val));
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+ iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
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+ ARRAY_SIZE(zero_val));
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iwl_pcie_txq_unmap(trans, txq_id);
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