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@@ -115,9 +115,10 @@ Before jumping into the kernel, the following conditions must be met:
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External caches (if present) must be configured and disabled.
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- Architected timers
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- CNTFRQ must be programmed with the timer frequency.
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- If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
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- set where available.
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+ CNTFRQ must be programmed with the timer frequency and CNTVOFF must
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+ be programmed with a consistent value on all CPUs. If entering the
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+ kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
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+ available.
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- Coherency
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All CPUs to be booted by the kernel must be part of the same coherency
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@@ -130,30 +131,46 @@ Before jumping into the kernel, the following conditions must be met:
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the kernel image will be entered must be initialised by software at a
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higher exception level to prevent execution in an UNKNOWN state.
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+The requirements described above for CPU mode, caches, MMUs, architected
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+timers, coherency and system registers apply to all CPUs. All CPUs must
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+enter the kernel in the same exception level.
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+
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The boot loader is expected to enter the kernel on each CPU in the
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following manner:
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- The primary CPU must jump directly to the first instruction of the
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kernel image. The device tree blob passed by this CPU must contain
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- for each CPU node:
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-
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- 1. An 'enable-method' property. Currently, the only supported value
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- for this field is the string "spin-table".
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-
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- 2. A 'cpu-release-addr' property identifying a 64-bit,
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- zero-initialised memory location.
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+ an 'enable-method' property for each cpu node. The supported
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+ enable-methods are described below.
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It is expected that the bootloader will generate these device tree
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properties and insert them into the blob prior to kernel entry.
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-- Any secondary CPUs must spin outside of the kernel in a reserved area
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- of memory (communicated to the kernel by a /memreserve/ region in the
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+- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
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+ property in their cpu node. This property identifies a
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+ naturally-aligned 64-bit zero-initalised memory location.
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+
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+ These CPUs should spin outside of the kernel in a reserved area of
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+ memory (communicated to the kernel by a /memreserve/ region in the
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device tree) polling their cpu-release-addr location, which must be
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contained in the reserved region. A wfe instruction may be inserted
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to reduce the overhead of the busy-loop and a sev will be issued by
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the primary CPU. When a read of the location pointed to by the
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- cpu-release-addr returns a non-zero value, the CPU must jump directly
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- to this value.
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+ cpu-release-addr returns a non-zero value, the CPU must jump to this
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+ value. The value will be written as a single 64-bit little-endian
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+ value, so CPUs must convert the read value to their native endianness
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+ before jumping to it.
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+
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+- CPUs with a "psci" enable method should remain outside of
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+ the kernel (i.e. outside of the regions of memory described to the
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+ kernel in the memory node, or in a reserved area of memory described
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+ to the kernel by a /memreserve/ region in the device tree). The
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+ kernel will issue CPU_ON calls as described in ARM document number ARM
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+ DEN 0022A ("Power State Coordination Interface System Software on ARM
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+ processors") to bring CPUs into the kernel.
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+
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+ The device tree should contain a 'psci' node, as described in
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+ Documentation/devicetree/bindings/arm/psci.txt.
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- Secondary CPU general-purpose register settings
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x0 = 0 (reserved for future use)
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