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@@ -73,8 +73,32 @@
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#define MSR_P6_EVNTSEL0 0x00000186
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#define MSR_P6_EVNTSEL1 0x00000187
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-/* K7/K8 MSRs. Not complete. See the architecture manual for a more
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+/* AMD64 MSRs. Not complete. See the architecture manual for a more
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complete list. */
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+
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+#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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+#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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+#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
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+#define MSR_AMD64_IBSOPCTL 0xc0011033
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+#define MSR_AMD64_IBSOPRIP 0xc0011034
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+#define MSR_AMD64_IBSOPDATA 0xc0011035
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+#define MSR_AMD64_IBSOPDATA2 0xc0011036
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+#define MSR_AMD64_IBSOPDATA3 0xc0011037
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+#define MSR_AMD64_IBSDCLINAD 0xc0011038
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+#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
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+#define MSR_AMD64_IBSCTL 0xc001103a
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+
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+/* K8 MSRs */
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+#define MSR_K8_TOP_MEM1 0xc001001a
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+#define MSR_K8_TOP_MEM2 0xc001001d
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+#define MSR_K8_SYSCFG 0xc0010010
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+#define MSR_K8_HWCR 0xc0010015
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+#define MSR_K8_ENABLE_C1E 0xc0010055
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+#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
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+#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
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+#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
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+
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+/* K7 MSRs */
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#define MSR_K7_EVNTSEL0 0xc0010000
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#define MSR_K7_PERFCTR0 0xc0010004
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#define MSR_K7_EVNTSEL1 0xc0010001
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@@ -83,20 +107,10 @@
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#define MSR_K7_PERFCTR2 0xc0010006
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#define MSR_K7_EVNTSEL3 0xc0010003
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#define MSR_K7_PERFCTR3 0xc0010007
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-#define MSR_K8_TOP_MEM1 0xc001001a
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#define MSR_K7_CLK_CTL 0xc001001b
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-#define MSR_K8_TOP_MEM2 0xc001001d
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-#define MSR_K8_SYSCFG 0xc0010010
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-
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-#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
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-#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
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-#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
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-
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#define MSR_K7_HWCR 0xc0010015
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-#define MSR_K8_HWCR 0xc0010015
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#define MSR_K7_FID_VID_CTL 0xc0010041
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#define MSR_K7_FID_VID_STATUS 0xc0010042
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-#define MSR_K8_ENABLE_C1E 0xc0010055
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/* K6 MSRs */
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#define MSR_K6_EFER 0xc0000080
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