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@@ -25,32 +25,12 @@
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__CPUINIT
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/*
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- * Reset vector for secondary CPUs.
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+ * Boot code for secondary CPUs.
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*
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* First we turn on L1 cache coherency for our CPU. Then we jump to
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* shmobile_invalidate_start that invalidates the cache and hands over control
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* to the common ARM startup code.
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- * This function will be mapped to address 0 by the SBAR register.
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- * A normal branch is out of range here so we need a long jump. We jump to
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- * the physical address as the MMU is still turned off.
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*/
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- .align 12
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-ENTRY(shmobile_secondary_vector_scu)
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- mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
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- and r0, r0, #3 @ mask out cpu ID
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- lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
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- ldr r1, 2f
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- ldr r1, [r1] @ SCU base address
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- ldr r2, [r1, #8] @ SCU Power Status Register
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- mov r3, #3
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- bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
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- str r2, [r1, #8] @ write back
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-
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- ldr pc, 1f
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-1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
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-2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
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-ENDPROC(shmobile_secondary_vector_scu)
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-
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ENTRY(shmobile_boot_scu)
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@ r0 = SCU base address
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mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
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