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@@ -18,28 +18,42 @@
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/sched_clock.h>
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-#include <asm/mach/time.h>
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-#include <mach/bridge-regs.h>
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-#include <mach/hardware.h>
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/*
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- * Number of timer ticks per jiffy.
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+ * MBus bridge block registers.
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*/
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-static u32 ticks_per_jiffy;
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+#define BRIDGE_CAUSE_OFF 0x0110
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+#define BRIDGE_MASK_OFF 0x0114
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+#define BRIDGE_INT_TIMER0 0x0002
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+#define BRIDGE_INT_TIMER1 0x0004
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/*
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* Timer block registers.
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*/
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-#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
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-#define TIMER0_EN 0x0001
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-#define TIMER0_RELOAD_EN 0x0002
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-#define TIMER1_EN 0x0004
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-#define TIMER1_RELOAD_EN 0x0008
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-#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
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-#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
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-#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
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-#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
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+#define TIMER_CTRL_OFF 0x0000
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+#define TIMER0_EN 0x0001
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+#define TIMER0_RELOAD_EN 0x0002
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+#define TIMER1_EN 0x0004
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+#define TIMER1_RELOAD_EN 0x0008
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+#define TIMER0_RELOAD_OFF 0x0010
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+#define TIMER0_VAL_OFF 0x0014
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+#define TIMER1_RELOAD_OFF 0x0018
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+#define TIMER1_VAL_OFF 0x001c
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+
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+
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+/*
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+ * SoC-specific data.
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+ */
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+static void __iomem *bridge_base;
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+static u32 bridge_timer1_clr_mask;
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+static void __iomem *timer_base;
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+
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+
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+/*
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+ * Number of timer ticks per jiffy.
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+ */
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+static u32 ticks_per_jiffy;
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/*
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@@ -50,14 +64,14 @@ static DEFINE_CLOCK_DATA(cd);
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unsigned long long notrace sched_clock(void)
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{
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- u32 cyc = 0xffffffff - readl(TIMER0_VAL);
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+ u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
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return cyc_to_sched_clock(&cd, cyc, (u32)~0);
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}
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static void notrace orion_update_sched_clock(void)
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{
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- u32 cyc = 0xffffffff - readl(TIMER0_VAL);
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+ u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
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update_sched_clock(&cd, cyc, (u32)~0);
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}
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@@ -71,7 +85,7 @@ static void __init setup_sched_clock(unsigned long tclk)
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*/
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static cycle_t orion_clksrc_read(struct clocksource *cs)
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{
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- return 0xffffffff - readl(TIMER0_VAL);
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+ return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
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}
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static struct clocksource orion_clksrc = {
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@@ -101,23 +115,23 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
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/*
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* Clear and enable clockevent timer interrupt.
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*/
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- writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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+ writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
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- u = readl(BRIDGE_MASK);
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+ u = readl(bridge_base + BRIDGE_MASK_OFF);
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u |= BRIDGE_INT_TIMER1;
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- writel(u, BRIDGE_MASK);
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+ writel(u, bridge_base + BRIDGE_MASK_OFF);
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/*
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* Setup new clockevent timer value.
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*/
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- writel(delta, TIMER1_VAL);
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+ writel(delta, timer_base + TIMER1_VAL_OFF);
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/*
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* Enable the timer.
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*/
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- u = readl(TIMER_CTRL);
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+ u = readl(timer_base + TIMER_CTRL_OFF);
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u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
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- writel(u, TIMER_CTRL);
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+ writel(u, timer_base + TIMER_CTRL_OFF);
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local_irq_restore(flags);
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@@ -135,37 +149,38 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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/*
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* Setup timer to fire at 1/HZ intervals.
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*/
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- writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
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- writel(ticks_per_jiffy - 1, TIMER1_VAL);
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+ writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
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+ writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
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/*
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* Enable timer interrupt.
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*/
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- u = readl(BRIDGE_MASK);
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- writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
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+ u = readl(bridge_base + BRIDGE_MASK_OFF);
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+ writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
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/*
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* Enable timer.
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*/
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- u = readl(TIMER_CTRL);
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- writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
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+ u = readl(timer_base + TIMER_CTRL_OFF);
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+ writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
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+ timer_base + TIMER_CTRL_OFF);
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} else {
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/*
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* Disable timer.
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*/
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- u = readl(TIMER_CTRL);
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- writel(u & ~TIMER1_EN, TIMER_CTRL);
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+ u = readl(timer_base + TIMER_CTRL_OFF);
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+ writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
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/*
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* Disable timer interrupt.
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*/
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- u = readl(BRIDGE_MASK);
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- writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
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+ u = readl(bridge_base + BRIDGE_MASK_OFF);
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+ writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
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/*
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* ACK pending timer interrupt.
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*/
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- writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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+ writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
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}
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local_irq_restore(flags);
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@@ -185,7 +200,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
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/*
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* ACK timer interrupt and call event handler.
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*/
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- writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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+ writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
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orion_clkevt.event_handler(&orion_clkevt);
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return IRQ_HANDLED;
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@@ -197,31 +212,45 @@ static struct irqaction orion_timer_irq = {
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.handler = orion_timer_interrupt
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};
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-void __init orion_time_init(unsigned int irq, unsigned int tclk)
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+void __init
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+orion_time_set_base(u32 _timer_base)
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+{
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+ timer_base = (void __iomem *)_timer_base;
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+}
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+
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+void __init
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+orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
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+ unsigned int irq, unsigned int tclk)
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{
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u32 u;
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+ /*
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+ * Set SoC-specific data.
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+ */
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+ bridge_base = (void __iomem *)_bridge_base;
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+ bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
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+
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ticks_per_jiffy = (tclk + HZ/2) / HZ;
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/*
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- * Set scale and timer for sched_clock
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+ * Set scale and timer for sched_clock.
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*/
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setup_sched_clock(tclk);
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/*
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* Setup free-running clocksource timer (interrupts
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- * disabled.)
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+ * disabled).
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*/
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- writel(0xffffffff, TIMER0_VAL);
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- writel(0xffffffff, TIMER0_RELOAD);
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- u = readl(BRIDGE_MASK);
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- writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
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- u = readl(TIMER_CTRL);
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- writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
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+ writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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+ writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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+ u = readl(bridge_base + BRIDGE_MASK_OFF);
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+ writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
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+ u = readl(timer_base + TIMER_CTRL_OFF);
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+ writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
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clocksource_register_hz(&orion_clksrc, tclk);
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/*
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- * Setup clockevent timer (interrupt-driven.)
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+ * Setup clockevent timer (interrupt-driven).
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*/
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setup_irq(irq, &orion_timer_irq);
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orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
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